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Model_sim_6.6se_crack
- modelsim破解文件,这个找到的.需要大家一起用吧.-modelsim 6.6 crack
i2c
- i2c硬件程序,字节读、字节写，在modelsim6.0通过编译-the soft for i2c
Hmwxw5u8
- ModelSim6.2不能生成波形图的解决方案. 视频教程-ModelSim6.2 wave can not generate solutions. Video Tutorial!!!
edge_detection
- edge detection algorithm in verilog HDL, along with test bench file. compiled in modelsim6.1
ModelSim_SE_6.5_downloads_install_Configuration.ra
- 详细的介绍了modelsim的下载，破解，编译xilinx库，配置的问题，非常详细-Described in detail modelsim download, crack, the compiler library xilinx, configuration problems, in great detail
decoder
- A program for a simple decoder using ModelSim6
encoder
- A program for a simple encoder using ModelSim6
modelsim
- Modelsim6.0的应用教程以及一些注意事项。-Modelsim6.0 application tutorial and some notes.
modelsim6.0
- modelsim 中文使用手册，希望对想学习mldelsim的人有用-modelsim Chinese user manual, and they hope people who want to learn a useful mldelsim
m
- m序列生成文件，带有我自己写的仿真，结果在modelsim6.0f中生成正确。-m sequence generation file, written with my own simulation results generated in the modelsim6.0f correct.
Crack_ModelSim_SE_6.3d
- Modsim6.3 Crack and license
chuanbingzhuanhuan
- 可以实现串并转换功能，并且在modelsim6.0软件中成功仿真！-String and conversion functions can be achieved, and success in modelsim6.0 software emulation!
modelsim6.2b
- 使用Modelsim进行仿真，包括前仿真，与后仿真，使用Quartus 调用Modelsim进行仿真-Using Modelsim simulation, including the former emulation, and after the simulation, the simulation using Quartus call Modelsim
spi_master
- 用VHDL编写的一个SPI主机程序，SPI模块采用最常用的模式0方式（即CPOL=0,CPHA=0）通信。文件内含测试文档，已在Modelsim6.5上测试通过，可在FPGA上直接调用。-A SPI Master code edited by VHDL language,the SPI modul use 0 MODE(i.e CPOL=0,CPHA=0)to communicate with the SPI Slave.and there is a testbench in the file
UART-and-FPGA
- 基于FPGA的UART通信控制器 设计与实现持。用到modelsim6.1f环境模拟。-UART communication controller based on FPGA Design and Implementation of hold. Used modelsim6.1f environment simulation.
modelsim-SE-PLUS-6.5
- 自己总结的关于modelsim6.5的一些用法，希望可以与大家分享-something on the use of modelsim 6.5
modelsimse
- fpga仿真器modelsim6.5种子-modelsim6.5 seed
StopWatch
- 在Modelsim6.3c中编码，与Virtex-II Pro开发板连接实现秒表功能-In Modelsim6.3c encoding, and Virtex-II Pro development board to achieve a stopwatch function
fifo
- 在Modelsim6.3c中实现同步fifo-In Modelsim6.3c achieve synchronous fifo
Music_Player
- 基于Verilog的音乐播放器程序，在Modelsim6.5上仿真通过并可以在开发板上运行-Verilog-based music player program, in Modelsim6.5 through simulation and can be run on the development board