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32位-33M 从模式(target)PCI接口参考设计_lattice
- 32位/33M 从模式(target)PCI接口参考设计，Lattice提供。由于PCI时序较复杂，此设计仅能供参考-32 / route from the model (target) PCI reference design, Lattice provided. Because PCI timing more complicated, and the design for reference only
PCI_144
- -- PCI Target Interface Design for XC73144 -- -- Synopsys VHDL Solution using Xilinx XC7000 Library --- PCI Target Interface Design for XC73144 -- -- Synopsys VHDL Solution using Xilinx XC7000 Library
tmman_periph
- wince host 和 target PCI驱动程序，支持热插拔。target侧PCI驱动支持philips trimedia处理器-wince host and target PCI driver support Hot Swap. Target side PCI driver support philips trimedia Processor
PCI.Hot-Plug.Specification.v1.0
- PCI Hot-Plug Specification Revision 1.0 The primary objective of this specification is to enable higher availability of file and application servers by standardizing key aspects of the process of removing and installing PCI adapter cards while t
Pcit32vhdl
- PCI 32 target IP for Fpga/asic Designer
hgb_pci_host
- 内有一PCI 主 和PCI从，PCI TARGET 都是公开代码的，是工程文件，有仿真工程，使用说明。觉得好的就推荐一下。 本PCI_HOST目前支持： 1、 对目标PCI_T进行配置； 2、 对目标进行单周期读写； 3、 可以工作在33MHZ和66MHZ 4、 支持目标跟不上时插入最长10时钟的等待。 ALTERA的PCI竟然收费的！！！软件里面调试仿真了半天，终于调通了，到了下载就突然弹出窗口说包含了有限制的IP CORE，是限制使用的
mem32_to_pcitarget_verilog
- This design example shows how to implement interface between 32-bit pci target Altera megafunction instantiation and a 32-bit synchronous memory
DM642pci
- DM642 PCI q驱动 包括主机端和目标端-DM642 PCI q drive, including the host side and target side
pci_t
- verilog开发的PCI target模块，能完成配置空间的读写以及单次的memory读写，原创。-Verilog development of PCI target module, to complete the reading and writing, as well as the configuration space of a single memory read and write, originality. Ha ha
plx9054-localbus-cpld-vhdl-src
- PLX 公司 PLX9054 pci target controller local bus interface vhdl programe-PLX inc. PLX9054 pci target controller local bus interface vhdl programe
pci_target
- pci target design verilog file
mem64_to_pcitarget_verilog
- This design example shows possible interface between instantiation of Altera s 64-bit pci target megafunction and 64-bit synchronous memory -This design example shows possible interface between instantiation of Altera s 64-bit pci target megafunctio
pcitarget_disconnect_verilog
- This design shows how to implement a disconnect of a pci target instantiation of Altera s pci megafunction
pci_gr
- vhdl code for Simple PCI target interface
rd1008_rev03.4
- PCI Target 33M,32-BIT LATTICE DEVICE-PCI Target
pci_verilog_target
- 这是一个Verilog源代码写的PCI从设备参考设计。-This block is the Verilog source code for the Vantis 32 bit 33Mhz PCI Target Reference Design.
33M-(target)PCI-attice
- 32位33Mhz PCI接口程序设计参考，芯片是Lattice-This block is the top level Verilog module for the Vantis 32 bit 33Mhz PCI Target Reference Design.
PCI-Target-32-bit-_-66MHz-for-MachXO
- Evaluation Package for PCI Target 32-bit _ 66MHz for MachXO
dm-target
- PCI Backend - Handles the virtual fields found on the capability lists in the configuration space.
PCI-1716
- MATLAB xPc目标环境下的研华PCI数据采集卡驱动代码(MATLAB xPc driver code for Advantech PCI data acquisition card in target environment)