搜索资源列表
vhdl
- usb rtl code, to fpga or asic
i2c
- i2c rtl code , document, simulation
DesignofCANRTLlevel
- CAN RTL级设计,详细介绍了符合CAN协议的芯片级设计。-Design of CAN RTL level
spi
- SPI总线的RTL源代码，很好用，省掉你大量的工作量-the spi bus RTL Code
singt
- 用VHDL语言描述的用锁存器，加法计数器，ROM存储器构成的RTL图-VHDL language used to describe the use of latches, adding counters, ROM memory map consisting of RTL
RTL
- 对usb设备控制的ip核进行了重新设计并进一步优化-Usb device on the control of nuclear ip has been redesigned and further optimize
fft_rtl
- rtl实现的fft变换，经硬件测试其功能与altera的fftip核相近-fft transform based on rtl design
lab04
- RTL in Verilog (Vending Machine)
driver-rtl
- 8180的 linux驱动 提供linux内核支持802.11g的模块-driver to provide core support for 802.11g modules, linux based
book
- Verilog HDL与VHDL都是数字系统设计的硬件描述语言，VerilogHDL适合算法级，rtl，逻辑级，门级，而VHDL适合特大型的系统级设计。针对这些特点这两本书深入浅出的介绍了这两种语言。-Verilog HDL and VHDL design of digital systems is the hardware descr iption language, VerilogHDL suitable algorithm level, rtl, logic level, gate-lev
watch_dog_rtl_source
- Watchdog timer verilog RTL code
timer_rtl_source
- Timer verilog RTL code
i2c_master_slave_latest[1].tar
- I2C Core VHDL RTL Source Code for Synthesis
uart_0910
- uart串口传输的verilog RTL级源码，已通过仿真验证。文件主要包含发送、接受位处理，发送、接受字节帧处理，对学习串口通信的朋友很有帮助-uart serial transmission verilog RTL-level source code has been verified by simulation. File mainly contains the send, receive digital processing, sending, receiving bytes of fr
async_fifo
- verilog HDL写的异步fifo代码及测试平台，直接可用，可生成RTL代码-asynchronous fifo write verilog HDL code and test platform, directly available, can generate RTL code for
rtl
- ddr controller in verilog-ddr controller in verilog...............
RTL
- 用VHDL实现求两个数的最大公因数。数据路径和控制路径。-Seeking to use VHDL to achieve the greatest common factor of two numbers. Data path and control path.
8bit_RISC_CPU_RTL_Code
- 8位RISC CPU 内核源码(VERILOG版)-8 bit RSIC CPU RTL code(Verilog)