搜索资源列表
adc_verilog
- adc verilog 用verilog编写的sigma-delta adc例子 应用在计量类adc产品
verilogsigma-deltaadc
- 用verilog编写的sigma-deltaADC的源程序。-code of verilog for sigma delta ADC
sigmadelta_verilog_code
- sigma delta verilog code and testbench for you to do simulation
adc_spi
- dsp通过SPI接口数据采集 sigma-delta ADC采集程序-dsp through the SPI interface, data acquisition sigma-delta ADC acquisition program
Verilog-Code
- Verilog source code by James Patchell: - Delta Sigma Modulator for doing Digital->Analog Conversion - Aquad-bquad phase detector - Uart Reciever - Uart Transmitter - One shot
dac_sigma_delta
- verilog code for a 2nd order sigma delta modulator
delta-sigma-DAC
- 根据FPGA的∑-Δ D/A转换器的设计与实现策略，∑-Δ DAC的内部仅由2个10位的二进制加法器，1个10位的锁存器和一个D触发器组成，用FPGA实现时只需耗费极少的逻辑资源，即使用最小的FPGA也能实现。这是∑-Δ DAC实现的verilog语言-According to the FPGA Σ-Δ D/A converter design and implementation strategies, Σ-Δ DAC' s internal only by the two 10-bit
用verilog编写的sigma-delta adc例子
- 累加器实现艾哈空间哈卡哈尽快啊哈卡哈卡快捷回复哈哈哈看(Accumulator implementation)
VERILOG
- 基础的几个verilog代码实现，讲到case和task的使用。(basic verilog,use case and task ,very usual, i want some help to achieve the design of delta and sigma fractional_n divider.)