搜索资源列表
16bit-ALU
- 16位ALU。包括超前进位加减法器、大小比较、算术逻辑位移等运算-16-bit ALU. Including lookahead adder-subtractor, size comparison, arithmetic and logic operations displacement
verilog-source-codes
- the attached programs are source codes of 4-bit ring counter, 16x1 mux, 8x3 priority encoder, 4x16 decoder, full subtractor using two half subtractors
accsub
- 简单的加法器减法器程序代码，Verilog HDL初学者学习可以使用-Simple adder subtractor code, Verilog HDL beginners can use
Serial-borrow-eight-subtracte
- 本程序实现了串行借位的八位减法器，采用VHDL语言实现。-This program implements eight serial borrow subtractor, using VHDL language.
Exp-04-Subtractor---Copy
- experiment no 4 using matlab
sub
- subtractor vhdl code for fpga
adder_sub_TB
- adder/subtractor testbench
sub_1
- sub_1 subtractor 1 bit xxxxxxxxxxxx