搜索资源列表
uartfifo
- 串口收发程序，VHDL版本，适用于ALTERA的CPLD -Serial transceiver procedures, VHDL version
uartfifo
- 基于FPGA的串口发送源代码，通过FIFO能够发送一段字符串。-FPGA-based serial port source code, a string can be sent through the FIFO.
UartFIFO
- LPCARM串口无限FIFO的实现源码。-Serial FIFO implementation LPCARM unlimited source
uartfifo
- FPGA串口代码实现，带串口模块控制程序-Realization of UART in FPGA, with UART module control codes.
uartfifo
- 硬件描述语言，fifo数据存储模块，有讲述-Hardware descr iption language, fifo data storage module, there are about
uartfifo
- 用 Verilog语言编写的串口发送接收程序，带FIFO 已调试通过-Verilog language with sending and receiving serial program with debugging through the FIFO
uartfifo
- 一个串口和收发器，可以发送串口数据到电脑的串口程序中-A serial port and the transceiver can send serial data to the computer' s serial port program
uartfifo
- uart 通用异步收发器 verilog 代码，实现自收发功能，quartus运行有效。-uart universal asynchronous transceiver verilog code, since the transceiver function, quartus operating effectively.
uartfifo
- verilog实现的fifo到串口数据通信-verilog achieve fifo to the serial data communication
uartfifo
- 利用verilog开发的串口FIFO程序，比较基本，包含完整的工程-The verilog developed serial FIFO procedures, more basic, including the complete project
uartfifo
- 串口fifo的实现~实现了串口功能以及异步fifo，经过调试和功能仿真-The implementation of the serial fifo ~ serial port functionality as well as asynchronous fifo, after debugging and functional simulation
uartfifo
- 同步异步传输协议的应用通过调试助手向FPGA发送数据，然后再读出来，-Application of synchronous and asynchronous transmission protocol to send data to the FPGA debugging assistant, and then read out
uartfifo
- FPGA采用FIFO实现UART，对于大量异步数据的采集传输很有帮助-A usart design of FPGA using fifo,it can be used in massed asychronous data collect.
uartfifo
- 以Proasic3 Start kit开发板为平台，介绍了FIFO的基本功能。-ProASIC3 Start Kit development board as a platform to introduce the basic functions of the FIFO.
uartfifo
- 基于FIFO的串口发送机设计。主要实现一个串口发送器功能，该发送器的数据是从FIFO 中读取的。也就是说，只要FIFO 中有数据，串口发送器就会启动，将数据发送出-FIFO-based serial transmitter design. A serial transmitter function of the transmitter data is read from the FIFO. In other words, as long as there is data in the FIFO,
uartfifo
- 将产生的数据存入FIFO中并由串口发送出去。-The resulting data into the FIFO by the serial port to send out.
uartfifo
- 一个基于verilog的fifo的例子，由数据产生模块产生数据传到fifo中，然后同过发送模块将数据发到上位机上。-One based on the fifo verilog example, by the data generation module generates data to the fifo, and then sent over the same module sends data to the host computer.
uartfifo
- 该实验主要实现一个串口发送器功能， 该发送器的数据是从FIFO中读取的。也就是说，只要FIFO中有数据，串口发送器就会启动，将数据发送出去。 -The main experimental realization of a serial transmitter function, which sends the data is read the FIFO. In other words, as long as there is data in the FIFO, serial transmitt
uartfifo
- FPGA简单应用，VHDL程序，串口UART驱动程序，供学习参考。-FPGA and simple application, VHDL program, UART serial port driver, provide the reference for the study.
uartfifo
- fifo模式下的uart串口verilog的源程序-fifo mode serial uart verilog source