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SPI_AT45DB041B.rar
- 用verilog编写的SPI程序,SPI芯片是AT45DB041B.文件内包含程序仿真时的截图.包括read和wirte.,SPI prepared using Verilog procedures, SPI chip AT45DB041B. Document contains procedures for simulation screenshot. Including read and wirte.
EPM240_SCH_and_program.rar
- EPM240 cpld 原理图+程序。 Verilog HDL语言。 程序有正弦波发生器，ADC0804直流采样和显示，汉字滚动，交通灯，键盘，显示程序，计数器等等。,Schematic diagram+ EPM240 cpld procedures. Sine wave generator procedures, ADC0804 DC sampling and showed that Chinese scroll, traffic lights, keyboard, display pro
fifo
- 异步fifo，用Verilog编写，包含testbench，已经通过modelsim调试，内含文档和波形图-Asynchronous fifo, to prepare to use Verilog, including testbench, debug modelsim has passed, including documents and wave
VERILOG-jpeg
- 用Verilog语言在FPGA上实现JPEG图片的解码，附带testbench-With the Verilog language in the FPGA to achieve JPEG image decoding, with testbench
EPM240_analog_lcd_moudle_controller(sch_pcb_democo
- EPM240做的模拟屏控制器，有原理图（PDF）,PCB(PDF),手册（DOC）,程序（verilog），PIN文件。淘宝上有得买-EPM240 analog LCD moudle controller with schematic，PCB,demo code，handbook，pin assiment file。
risc
- 嵌入式risc处理器源码，包含设计文档，原理图，testbench，及外围接口，使用verilog实现。-Source embedded RISC processors, including design documents, schematics, testbench, and peripheral interfaces, the use of Verilog to achieve.
Tug-of-war-game
- 拔河游戏机制作的原理图PCB原理图。数字逻辑电路。-Tug-of-war game produced by PCB schematic schematic. Digital logic circuits.
fsk
- 数字通信中的FSK调制解调的原理和过程, 通过用Matlab 对这一过程的编程,分析信号在理想信道和加噪信道中传输时的时域图, 并用蒙特卡罗算法进行仿真。-Digital communications in FSK modulation and demodulation principle and process, through the use of Matlab in the process of programming, analysis of signals in the ideal c
alu
- 设计带进位算术逻辑运算单元，根据74LS181功能表，用Verilog HDL硬件描述语言编程实现ALU181的算术逻辑运算功能，编辑实验原理图，在算术逻辑单元原理图上，将其扩展为带进位的算术逻辑运算单元，对其进行编译，并设计波形对其进行仿真验证，最后下载验证-Design into the digital arithmetic logic operation unit, in accordance with menu 74LS181 with Verilog HDL hardware desc
guard_against_theft
- 利用XC9572－PQ44（Xilinx CPLD）制作的一款家用防盗报警器的Verilog源代码及原理图，当房门打开后，15秒内若没有按下Key1,则会自动拨打设定手机号（当然，要另连接一台手机）-Using XC9572-PQ44 (Xilinx CPLD) produced by a home burglar alarm of the Verilog source code and the schematic diagram, when the door opened, within 15
ALU8
- ALU算术逻辑单元，8位，含源程序以及仿真后的波形图-ALU arithmetic logic unit 8, including source code, as well as post-simulation waveform
traffic
- verilog编写的一个交通灯程序，利用状态机实现。压缩包内有说明文档，源代码及时序截图-verilog prepared a program of traffic lights, the use of state machine to achieve. Compressed packet, there are documentation, source code and timing Screenshots
weitongbu
- 关于锁相法位同步的VHDL实现，包括BLOCK图。-failed to translate
iqit(verilog)
- H.264算法中的反变换反量化部分的设计，能够实时处理720x576图像。-The IQIT part of H.264, which can process 720x576 image.
imageSample
- 这是一个图象传感器的数据采集程序，用Verilog语言编写，经测试通过，改程序可以作为图像数据采集参考，缩短开发时间。-This is an image sensor data collection procedures, with the Verilog language, has been tested and approved to change the image data acquisition procedure can be used as reference, to shorte
MPEG4Codec
- Mpeg4图象编解码算法原程序，基于VC。-Mpeg4 decoding algorithm for the original process image, based on VC.
des
- des解密加密的verilog源代码其中包含有测试源代码，仿真结果图-verilog des decrypt encrypted source code which includes testing the source code, Simulation results
OpenSource_H64
- gl850 usb hub原理图gl850 usb hubgl850 usb hub-gl850 usb hub
dds
- DDS数字式频率合成器 利用VERILOG实现，有modelsim仿真图-DDS digital frequency synthesizer using VERILOG realization, modelsim simulation diagram
verilog-HDL-learning
- 从零开始学verilog HDL ，包括Altera实验板原理图，xilinx实验板原理图和一些实验源程序-From scratch learn verilog HDL, including Altera experimental board schematic, xilinx test board schematics and source code of some experiments