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my_design_frequency
- 在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号是最重要的信号之一。 下面我们介绍分频器的 VHDL 描述，在源代码中完成对时钟信号 CLK 的 2 分频， 4 分频， 8 分频， 16 分频。 这也是最简单的分频电路，只需要一个计数器即可。-in digital circuits, and often the need for higher frequency for the clock frequency operation, th
clk-div
- VHDL code for a clock divider by 27 circuit with a resulting waveform with 50％ duty cycle..
clock_divider
- This code contains the simple program that can be used for the clock divider to set any desireable clock from the master clock.
clk_div
- Thia is VHDL code for clock divider
divider
- a clock divider vhdl code
clock-divider
- VHDL code for clock divider circuit. There are two modules: one output divide by 4 and other outputs divide by 6
Package
- Package consists of two pdf files: i)cdr project: theory and implementation of vhdl ii)I2C bus controller: xilinx implementation of uC interface on CPLD Package consists of 7 vhdl files: string_detector: detects the continuous string of 11
Dll-Files
- clock divider code for vhdl
Clockdivider
- VHDL CODE FOR CLOCK DIVIDER