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fpga-dm9000a
- 一个项目工程，硬件包含XINLINX FPGA，配置FLASH，串口，SDRAM,与以太网芯片DM9000A，实现数据采集，以太网传输，电路验证完全正确，请放心使用，SPARTAN 3E 的BGA引脚320个，不容易布板，可以参考使用的。要FPGA实现网络通信也可以参考电路，B因为产品升级了所以公开原来的电路的。 -A project engineering, hardware contains XINLINX FPGA, configuration FLASH, serial port, SD
基于模糊神经网络的自适应预失真功放
- 基于模糊神经网络的自适应预失真功放。DPD功放模型的研究。-Based on fuzzy neural network adaptive predistortion power amplifier. DPD amplifier modeling.
CyclonePLL
- Cyclone™ FPGA具有锁相环（PLL）和全局时钟网络，提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出，进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件，就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。 PLL常用于同步内部器件时钟和外部时钟，使内部工作的时钟频率比外部时钟更高，时钟延迟和时钟偏移最小，减小或调整时钟
seven
- 这是我在ISP编程实验中独立编写的采用结构化描述的一个七人表决器，通过独特的3次映射一位全加器的方法从而实现七人表决器的功能，与网络上任何其他的七人表决器源码决无雷同。-This is my ISP programming in an independent experiment using a structured, prepared as described in a seven-member voting machine, through a unique 3 times a full a
Proteus
- protus的人们必备，是从网络上摘录的经典-people must protus is extracted from the network on a classic
MTDB_SYSTEM_CD_V1.0
- ALTERA Nios II Embedded Evaluation Kit开发板制造商(terasic)提供的多媒体显示板（Terasic Multimedia Touch Panel Daughter Board (MTDB)）扩展开发包。 里为有两个开源的例子 1.MTDB_SD_Card_Audio,从SD卡中读取WAV文件然后通过DA播放，这个对不SD Card的初学者非常的有用，可以知道使用FPGA SPI来读写SD CARD。 2.MTDB_Systhesiz
sale
- 关于自动售货机的报告，内有源程序和DC综合网表图-Report on the vending machine with a DC source and an integrated network chart
mesh_dft
- 自己写一个关于维mesh结构的noc网络，verilog，仿真结果无误。-Write their own structure on the noc-dimensional mesh network, verilog, accurate simulation results.
web
- 模拟网络串行通信 近期对计算机间通信比较感兴趣，同时研究usb通信原理，起步为串行通信于是想为更好地理解其机理做一定基础性研究，故做了异步串行通信设计实验。 经过QUARTUS验证，获得了一等奖！-Simulation of the recent serial communication network between the communication of more interested in computers, communications usb at the same time
stackfiles
- VHDL IP Stack: This IP stack for an FPGA is a complex design because of the number of layers and the complexity of each that is required. It is limited to 10Mb/s operation and is designed for a full duplex switched network. It implements the lower la
SunFiles
- vhdl network links and main key for installation
CPU_Architecture
- Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks. External hardware accelerator is used for network packet processing. The common netw
AES
- This the source code of AES algorithm which is used in network security.-This is the source code of AES algorithm which is used in network security.
DES
- This is verilog source code for DES(Data Encryption standard) which is used in network security.
B_PON_OLT_VHDL
- ATM-PON(Passive Optical Network) OLT vdhl proj.file
4by4
- 4输入，4输出，clos网络所用，有利于连接处理器和处理器，处理器和存储器传输数据。-4 inputs, 4 outputs, clos network use is conducive to connecting the processor and processor, processor and memory to transfer data.
fjq4
- 光纤通信以其损耗低、高带宽、抗电磁干扰、保密性好等优点越来越多地应用在视频通信中[1～ 5 ]. 针对 光纤综合业务传输平台, 本文提出了一种将三路视频信息复用为一路视频信息的数字复接器的硬件电路 设计. 提高了传输容量和传输效率, 达到抗干扰、抗噪声的能力, 从而改善了传输平台的环境适应性及工作 性能. 该复接器硬件电路的设计采用EDA 技术, 以FPGA 器件为载体, 使用VHDL 硬件描述语言进行电路-Optical fiber communication with its l
aaccddeeff
- 基于模糊神经网络的自适应预失真功放。DPD功放模型的研究。-Based on fuzzy neural network adaptive predistortion power amplifier. DPD amplifier modeling.
fir_filter
- 实现滤波器的功能，有限冲激响应（FIR）数字滤波器和无限冲激响应（IIR）数字滤波器广泛应用于数字信号处理系统中。IIR数字滤波器方便简单，但它相位的非线性，要求采用全通网络进行相位校正，且稳定性难以保障。FIR滤波器具有很好的线性相位特性，使得它越来越受到广泛的重视。-Realize the filter function, finite impulse response (FIR) digital filters and infinite impulse response (IIR) dig
HDLC_VHDL
- 用VHDL实现从以太网到并行数据以及从并行数据到以太网的HDLC成帧解帧.附详细代码说明,方便阅读.可方面移植到Altera及Xilinx等厂家芯片,是做基于FPGA的以太网设计的好资料-Achieved using VHDL and parallel data from the Ethernet to parallel data from the HDLC framing solution to Ethernet frames. Attached detailed code instructi