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husw
- 用VHDL语言设计维特比 解码器 是VHDL原代码用ModelSim XE III 6.3c软件实现仿真-Language Design with VHDL Viterbi decoder is the VHDL source code with ModelSim XE III 6.3c software simulation
Viterbi_decoder
- Viterbi译码器的编解码器的设计 用Verilog实现-Viterbi decoder。Verilog
viterbi
- viterbi decoder with convolutional encoder
dafeldib2004
- In this document - decoder Viterbi on VHDL with low power architecture.
viterbi213
- 编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现，包含整个QuartusＩＩ的工程文件，解码方式为寄存器交换法-Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange