搜索资源列表
afifo
- verilog编写的异步FIFO代码，功能仿真时是正确的。-verilog code written in asynchronous FIFO, functional simulation is the right time.
sfifo
- verilog编写的同步FIFO，功能仿真完全正确，大家可以参考下。-verilog write synchronization FIFO, functional simulation completely correct, we can refer to the next.
16_64_proteus
- 本程序利用单片机AVR Mega8设计一16*64点阵式时钟显示屏。滚动显示现在的时间，显示字 符：“现在时间：**小时：**分：**秒”； 2 电子钟有暂停、开始计时、“小时”调整、“分钟”调整功能(小时、分钟调整以1为步进)； 3有proteus仿真 -This procedure used to design a microcontroller AVR Mega8 16* 64 dot matrix clock display. The time now scroll
RADARSimulation
- 雷达仿真的源程序，功能齐全，添加了界面，易于使用。-Radar Simulation of the source, fully functional, add the interface easy to use.
file.vec
- 对QUARTUS进行功能仿真时，需要输入自定义或者matlab生成的信号，此文件就是仿真需要的向量文件（.vec）,格式固定，可以仿照这个写，内含说明-Functional simulation of QUARTUS, you need to enter a custom or matlab generated signal, this file is required simulation vector file (. Vec), fixed format, you can follow th
Altera_FPGA_develop(QuartusII_7.2_ModelSim_6.5).ra
- Altera FPGA开发说明（QuartusII 7.2 & ModelSim 6.5）.pdf 建立和编译QII项目 modelsim功能仿真 QII引脚分配 modelsim时序仿真（建立Altera仿真库） QII下载 -Altera FPGA Development Descr iption (QuartusII 7.2 & ModelSim 6.5). Pdf project to establish and build QII QII pin ass
model_adder
- 包括一个基于Quartusii的加法器工程，以及基于ModelSim的前仿真、综合后功能仿真和布局布线后时序仿真的完整例程及testbench文件，吐血推荐，非常有用！-Includes an adder based Quartusii works, and the first based on ModelSim simulation, synthesis functional simulation and post layout timing simulation after complete
modelsim-timing-analysis
- 自己整理的一个关于如何使用modelsim进行功能仿真，时序仿真和布局布线的后仿真的文档，例子是抄的，针对的版本是modelsim se6.2b-Their finishing a feature on how to use modelsim for simulation, timing simulation and post-layout simulation of the document, copy the example is for the version of modelsim se
The-digital-Multimeter
- 计并制作一台具有直流电压、交流电压和电阻测量功能的智能数字万用表.- This design introduces the design and research for 4 3/4 Digit DMM Circuit integrally and systemically. he article mainly introduces the performance Characteristic of MAX134, inside structure, digital interfac
communication-system
- 介绍了通信系统中各种功能仿真的一些源代码和案例-Describes the simulation of communication systems in the various functions of some source code and case
fqsrd
- 对传感器设备的功能仿真模型源代码，可用于CGF系统，属人工智能领域-The function of the sensor device simulation model source code, can be used for CGF systems are artificial intelligence
cpld_10fenpin
- 针对cpld芯片采用verilog编程实现的10分频程序。附带其功能仿真文件。-For cpld chip verilog programming of 10 frequency program. With its functional simulation file.
basegate
- verilog的基本门电路描述 附带功能仿真波形-verilog descr iption of the basic gate circuit functional simulation waveforms with
2
- EDA的课程设计，利用VHDL语言、PLD设计基于FPGA的出租车计费系统，选用ALTERA公司低功耗、低成本、高性能的FPGA芯片EPF10K10，以MAX+PLUSⅡ软件作为开发平台，设计了出租车计费器系统程序并进行了编译，功能仿真和下载。使其实现计费以及预置和模拟汽车启动、加速、停止、暂停等功能，并动态扫描显示车费数目。-EDA curriculum design, the use of VHDL language, PLD design FPGA-based taxi billing s
verilog
- 用verilog语言进行状态机的时序与功能仿真-Verilog state machine language with timing and functional simulation
Buck
- 降压dc变换器输出功能仿真，根据可控晶闸管调节电压的压降，实现降压电路，采用pwm波控制。-buck DC Converter
LCD_VHDL
- 基于quartus ii 开发软件的LCD控制工程文件，含vhdl语言编写的程序，及时序和功能仿真文件。-Quartus ii software development based on the LCD control engineering documents, including a program written in vhdl, and functional and timing simulation files.
zq_100us
- 利用VHDL实现偶数分频，设计了一种能够实现等占空比的任意偶数分频、等占空比任意奇数分频、不等占空比的任意半整数分频的较为通用的分频器,并通过QuartusII进行了功能仿真。 -Use VHDL to achieve an even frequency, designed to achieve such a duty cycle of any even frequency, such as the duty cycle divide any odd number, ranging from
pll
- verilog硬件描述语言实现数字锁相环功能仿真,-Digital phase-locked loop using verilog
text
- 序列检测器可用于检测一组或多组由二进制码组成的脉冲序列信号。本系统用状态机来实现序列（1110010）的序列检测器的设计，若系统检测到串行序列 1110010 则输出为 1 ,否则输出为 0 ，并对其进行波形和功能仿真。-Sequence detection can be used to detect one or more groups formed by the binary code pulse train signal. The system implemented by the st