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Lab3_mux24a
- 4位2选1多路选择器的设计与实现。nexy3开发板。本实验中用Verilog语句来描述。-Xilinx ISE 12.3.nexy3.
vhdl
- 通过VHDL语言，实现简单的多路选择器、串行加法器、并行加法器、计数器-By VHDL language, a simple multiple-choice, serial adder, parallel adder, counter
exp-CPU
- 实现简单的CPU通路，包括存储器、指令译码、多路选择器等功能部件-Simple CPU access （by google）
chap12
- 16个常用HDL编码打包上传 包括记数器，多路选择器，全加/半加器等，均通过modsim验证-16 commonly used HDL coding package upload includes counter, MUX, all add/semi-add, etc., are adopted to verify modsim
mux2_1
- 利用QuartusⅡ完成2选1多路选择器的文本编辑输入和仿真测试等步骤，给出仿真波形。-Use QuartusⅡ completed 2-to-1 multiplexer input text editing and simulation testing and other steps, given the simulation waveform.
erxuanyiduoluxuanzeqi_no_maoxian
- 二选一多路选择器的verilog实现。VHDL，单片机开发程序，数字逻辑与处理器基础实验，你懂d。-Choose one multiplexer selector verilog implementation. VHDL, MCU development program, the digital logic and processor basic experiment, you know d.
sixuanyiduoluxuanzeqi_verilog
- 四选一多路选择器的verilog实现。VHDL，单片机开发程序，数字逻辑与处理器基础实验，你懂d。-4 election more than one way selector verilog implementation. VHDL, MCU development program, the digital logic and processor basic experiment, you know d.
thecode
- 基于FPGA的多路选择器程序，非常适合初级菜鸟学习使用入门程序，欢迎大家下载学习-FPGA multiplexer based procedures, very suitable for learning to use primary rookie entry procedures, are welcome to download the learning
mux21
- 二选一多路选择器的设计压缩包, 采用原理图方式和VHDL方式,quartusII 软件设计, 包含各种设计文件及目标下载文件.-mux21 design package, adopts the principle diagram method and VHDL, quartusII design software, download file contains all kinds of design documents and target.
max41a
- 用原理图方式实现4选1多路选择器，进行编译、综合、仿真测试等步骤-Schematic ways with 4-to-1 multiplexer, compile, synthesis, simulation testing and other steps
Ex09_selector
- 多路选择器，verilog hdl 语言实现-selector ，verilog hdl
mux21
- 32位多路选择器。输入信号有三个sel,a,b，当sel为0时，输出与a信号相同，为1时，输出与b信号相同-Complete a 32 bit multi-channel data selector
2_MUX_4_1_vt
- verilog HDL 编程 二选一多路选择器 带仿真文件-this is a verilog module.it have the fanction of selet the signal form two signals.
e1
- 清华大学电子系 组合逻辑实验 包括多路选择器设计，译码器设计，4位加法器设计-Tsinghua University, Department of Electronics, combinational logic experimental design includes multiplexer, decoder design, four adder design
compare
- 八位字节比较器，四选一多路选择器，二分频电路-Octet comparator 4 election more than one way selector, the second divider circuit
multiselectors-and-comparators
- 本压缩包包括四选一多路选择器、1位二进制比较器、2选1多路选择器、4位等值比较器、D触发器和奇偶校验电路-1 in 4 multiselector，D trigger,1 in 2 selector, 4 bit comparator, parity checking, 1bit comparator.
multichannel-selector
- 本程序实现了二选一多路选择器的硬件功能，采用VHDL语言编写而成。-This program implements a second election multiplexer hardware function, written in VHDL language.
电子设计自动化
- EDA中组合逻辑电路设计一个多路选择器VHDL程序的设计以及讲解(EDA combinational logic circuit design, a multiplexer, VHDL program design and explanation)
DPWM
- 用Verilog实现数字脉宽调制模块，主要模块有锁相环、计数器、多路选择器(The digital pulse width modulation module is realized by Verilog. The main modules are PLL, counter and multiplexer)
mux21
- 多路选择器的设计代码及仿真验证，还有激励文件。