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asyn_fifo
- 本文同步FIFO为TPRAM（两端口RAM，一读一写）。有详细verilog 程序以及说明-FIFO divided by clock domain can be divided into synchronous and asynchronous FIFO FIFO, FIFO read and write only one clock synchronous, asynchronous FIFO read and write were a clock. FIFO divided by