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seqdet
- Verilog编写的有限状态机的程序,实现对一二进制序列的检测,该有限状态机提供8个状态的,可以任意修改,作为测试。-Verilog written procedures for finite state machines to achieve the detection of a binary sequence, the finite state machine with 8 states, and can be freely modified, as a test.