资源列表
ref-ddr-sdram-vhdl
- 用VHDL编写DDR SDRAM Controller的源代码- Compiles DDR SDRAM Controller with VHDL the source code
jtag0
- 本程序使用vhdl编写的jtag接口实现程序,其中有些功能未能实现,希望有人能够帮忙完善!-vhdl the procedures used to prepare the jtag interface procedures, which some of them did not materialize, hope someone can help perfect!
VHDL学习手册
- VHDL学习手册-VHDL study manual
靳远-源程序
- 几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码-several VHDL source code, and in my preparation of a five pipelined RISC CPU code
whole
- ov7620的CPLD采集程序,VHDL语言-ov7620 CPLD acquisition procedures, VHDL
8255new
- vhdl实现8255,可重用,ALATEK公司提供验证,用说明文档-achieve VHDL 8255, reusable, ALATEK companies to provide certification, with documentation
16位乘法器
- 自已写的一个16X16的乘法器,速度比较慢。初学者练习练习!-own writing an audio Multiplier, speed is relatively slow. Beginners practice practice!
sopc
- altera推出的基于它们fpga和cpld的构建嵌入式系统的新技术sopc的介绍。其集成在quartus II中-ALTERA due to launch them and they simply cpld Construction of the new Embedded System Technology sopc briefing. Its integrated into the Quartus II
rtl
- 用verilog编写的网卡芯片rtl级。前仿后仿都通过了,可以在modelsim上运行察看-verilogrtl After the former imitation through imitation, it can run on the look modelsim