文件名称:ethernet_tri_mode_latest.tar
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./trunk/
./trunk/bench/
./trunk/bench/verilog/
./trunk/bench/verilog/altera_mf.v
./trunk/bench/verilog/User_int_sim.v
./trunk/bench/verilog/host_sim.v
./trunk/bench/verilog/reg_int_sim.v
./trunk/bench/verilog/tb_top.v
./trunk/bench/verilog/Phy_sim.v
./trunk/start.tcl
./trunk/rtl/
./trunk/rtl/verilog/
./trunk/rtl/verilog/eth_miim.v
./trunk/rtl/verilog/TECH/
./trunk/rtl/verilog/TECH/xilinx/
./trunk/rtl/verilog/TECH/xilinx/CLK_DIV2.v
./trunk/rtl/verilog/TECH/xilinx/CLK_SWITCH.v
./trunk/rtl/verilog/TECH/xilinx/duram.v
./trunk/rtl/verilog/TECH/altera/
./trunk/rtl/verilog/TECH/altera/CLK_DIV2.v
./trunk/rtl/verilog/TECH/altera/CLK_SWITCH.v
./trunk/rtl/verilog/TECH/altera/duram.v
./trunk/rtl/verilog/TECH/CLK_DIV2.v
./trunk/rtl/verilog/TECH/CLK_SWITCH.v
./trunk/rtl/verilog/TECH/duram.v
./trunk/rtl/verilog/afifo.v
./trunk/rtl/verilog/MAC_top.v
./trunk/rtl/verilog/RMON.v
./trunk/rtl/verilog/miim/
./trunk/rtl/verilog/miim/eth_clockgen.v
./trunk/rtl/verilog/miim/timescale.v
./trunk/rtl/verilog/miim/eth_shiftreg.v
./trunk/rtl/verilog/miim/eth_outputcontrol.v
./trunk/rtl/verilog/header.v
./trunk/rtl/verilog/RMON/
./trunk/rtl/verilog/RMON/RMON_dpram.v
./trunk/rtl/verilog/RMON/RMON_addr_gen.v
./trunk/rtl/verilog/RMON/RMON_ctrl.v
./trunk/rtl/verilog/MAC_rx/
./trunk/rtl/verilog/MAC_rx/CRC_chk.v
./trunk/rtl/verilog/MAC_rx/Broadcast_filter.v
./trunk/rtl/verilog/MAC_rx/MAC_rx_ctrl.v
./trunk/rtl/verilog/MAC_rx/MAC_rx_add_chk.v
./trunk/rtl/verilog/MAC_rx/MAC_rx_FF.v
./trunk/rtl/verilog/MAC_tx.v
./trunk/rtl/verilog/Phy_int.v
./trunk/rtl/verilog/Clk_ctrl.v
./trunk/rtl/verilog/MAC_rx.v
./trunk/rtl/verilog/MAC_tx/
./trunk/rtl/verilog/MAC_tx/flow_ctrl.v
./trunk/rtl/verilog/MAC_tx/MAC_tx_addr_add.v
./trunk/rtl/verilog/MAC_tx/MAC_tx_Ctrl.v
./trunk/rtl/verilog/MAC_tx/MAC_tx_FF.v
./trunk/rtl/verilog/MAC_tx/Ramdon_gen.v
./trunk/rtl/verilog/MAC_tx/CRC_gen.v
./trunk/rtl/verilog/reg_int.v
./trunk/syn/
./trunk/syn/syn_altrea.prj
./trunk/syn/syn_xilinx.prj
./trunk/syn/syn.prj
./trunk/sim/
./trunk/sim/rtl_sim/
./trunk/sim/rtl_sim/modsim_sim/
./trunk/sim/rtl_sim/modsim_sim/data/
./trunk/sim/rtl_sim/modsim_sim/data/10Mbps_duplex.vec
./trunk/sim/rtl_sim/modsim_sim/data/46-80.ini
./trunk/sim/rtl_sim/modsim_sim/data/target_mac_check.vec
./trunk/sim/rtl_sim/modsim_sim/data/1000Mbps_duplex.vec
./trunk/sim/rtl_sim/modsim_sim/data/CPU.vec
./trunk/sim/rtl_sim/modsim_sim/data/46-46.ini
./trunk/sim/rtl_sim/modsim_sim/data/flow_ctrl.vec
./trunk/sim/rtl_sim/modsim_sim/data/46-100.ini
./trunk/sim/rtl_sim/modsim_sim/data/source_mac_replace.vec
./trunk/sim/rtl_sim/modsim_sim/data/batch.dat
./trunk/sim/rtl_sim/modsim_sim/data/48-48.ini
./trunk/sim/rtl_sim/modsim_sim/data/47-47.ini
./trunk/sim/rtl_sim/modsim_sim/data/100Mbps_duplex.vec
./trunk/sim/rtl_sim/modsim_sim/data/config.ini
./trunk/sim/rtl_sim/modsim_sim/data/46-50.ini
./trunk/sim/rtl_sim/modsim_sim/bin/
./trunk/sim/rtl_sim/modsim_sim/bin/sim.mod
./trunk/sim/rtl_sim/modsim_sim/bin/ip_32W_check.dll
./trunk/sim/rtl_sim/modsim_sim/bin/vlog-rtl.list
./trunk/sim/rtl_sim/modsim_sim/bin/com.mod
./trunk/sim/rtl_sim/modsim_sim/bin/sim_only.mod
./trunk/sim/rtl_sim/modsim_sim/bin/ip_32W_gen.dll
./trunk/sim/rtl_sim/modsim_sim/script/
./trunk/sim/rtl_sim/modsim_sim/script/set_stimulus.tcl
./trunk/sim/rtl_sim/modsim_sim/script/batch_mode.tcl
./trunk/sim/rtl_sim/modsim_sim/script/run.tcl
./trunk/sim/rtl_sim/modsim_sim/script/start_verify.tcl
./trunk/sim/rtl_sim/modsim_sim/script/filesel.tcl
./trunk/sim/rtl_sim/modsim_sim/script/set_reg_data.tcl
./trunk/sim/rtl_sim/modsim_sim/script/run_proc.tcl
./trunk/sim/rtl_sim/modsim_sim/script/user_lib.tcl
./trunk/sim/rtl_sim/modsim_sim/log/
./trunk/sim/rtl_sim/modsim_sim/log/ncsim.log
./trunk/sim/rtl_sim/ncsim_sim/
./trunk/sim/rtl_sim/ncsim_sim/data/
./trunk/sim/rtl_sim/ncsim_sim/data/10Mbps_duplex.vec
./trunk/sim/rtl_sim/ncsim_sim/data/target_mac_check.vec
./trunk/sim/rtl_sim/ncsim_sim/data/1000Mbps_duplex.vec
./trunk/sim/rtl_sim/ncsim_sim/data/CPU.vec
./trunk/sim/rtl_sim/ncsim_sim/data/flow_ctrl.vec
./trunk/sim/rtl_sim/ncsim_sim/data/source_mac_replace.vec
./trunk/sim/rtl_sim/ncsim_sim/data/batch.dat
./trunk/sim/rtl_sim/ncsim_sim/data/100Mbps_duplex.vec
./trunk/sim/rtl_sim/ncsim_sim/data/config.ini
./trunk/sim/rtl_sim/ncsim_sim/data/46-50.ini
./trunk/sim/rtl_sim/ncsim_sim/bin/
./trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_check_vpi.dll
./trunk/sim/rtl_sim/ncsim_sim/bin/sim.nc
./trunk/sim/rtl_sim/ncsim_sim/bin/com.nc
./trunk/sim/rtl_sim/ncsim_sim/bin/sim_only.nc
./trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_check.dll
./trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_gen_vpi.dll
./trunk/sim/rtl_sim/ncsim_sim/bin/vlog.list
./trunk/sim/rtl_sim/ncsim_sim/bin/cds.lib
./trunk/sim/rtl_sim/ncsim_sim/bin/config.ini
./trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_gen.dll
./trunk/sim/rtl_sim/ncsim_sim/bin/hdl.var
./trunk/sim/rtl_sim/ncsim_sim/script/
./trunk/sim/rtl_sim/ncsim_sim/script/set_stimulus.tcl
./trunk/sim/rtl_sim/ncsim_sim/script/batch_mode.tcl
./trunk/sim/rtl_sim/ncsim_sim/script/run.tcl
./trunk/sim/rtl_sim/ncsim_sim/script/start_verify.tcl
./trunk/sim/rtl_sim/ncsim_sim/script/filesel.tcl
./trunk/sim/rtl_sim/ncsim_sim/script
./trunk/bench/
./trunk/bench/verilog/
./trunk/bench/verilog/altera_mf.v
./trunk/bench/verilog/User_int_sim.v
./trunk/bench/verilog/host_sim.v
./trunk/bench/verilog/reg_int_sim.v
./trunk/bench/verilog/tb_top.v
./trunk/bench/verilog/Phy_sim.v
./trunk/start.tcl
./trunk/rtl/
./trunk/rtl/verilog/
./trunk/rtl/verilog/eth_miim.v
./trunk/rtl/verilog/TECH/
./trunk/rtl/verilog/TECH/xilinx/
./trunk/rtl/verilog/TECH/xilinx/CLK_DIV2.v
./trunk/rtl/verilog/TECH/xilinx/CLK_SWITCH.v
./trunk/rtl/verilog/TECH/xilinx/duram.v
./trunk/rtl/verilog/TECH/altera/
./trunk/rtl/verilog/TECH/altera/CLK_DIV2.v
./trunk/rtl/verilog/TECH/altera/CLK_SWITCH.v
./trunk/rtl/verilog/TECH/altera/duram.v
./trunk/rtl/verilog/TECH/CLK_DIV2.v
./trunk/rtl/verilog/TECH/CLK_SWITCH.v
./trunk/rtl/verilog/TECH/duram.v
./trunk/rtl/verilog/afifo.v
./trunk/rtl/verilog/MAC_top.v
./trunk/rtl/verilog/RMON.v
./trunk/rtl/verilog/miim/
./trunk/rtl/verilog/miim/eth_clockgen.v
./trunk/rtl/verilog/miim/timescale.v
./trunk/rtl/verilog/miim/eth_shiftreg.v
./trunk/rtl/verilog/miim/eth_outputcontrol.v
./trunk/rtl/verilog/header.v
./trunk/rtl/verilog/RMON/
./trunk/rtl/verilog/RMON/RMON_dpram.v
./trunk/rtl/verilog/RMON/RMON_addr_gen.v
./trunk/rtl/verilog/RMON/RMON_ctrl.v
./trunk/rtl/verilog/MAC_rx/
./trunk/rtl/verilog/MAC_rx/CRC_chk.v
./trunk/rtl/verilog/MAC_rx/Broadcast_filter.v
./trunk/rtl/verilog/MAC_rx/MAC_rx_ctrl.v
./trunk/rtl/verilog/MAC_rx/MAC_rx_add_chk.v
./trunk/rtl/verilog/MAC_rx/MAC_rx_FF.v
./trunk/rtl/verilog/MAC_tx.v
./trunk/rtl/verilog/Phy_int.v
./trunk/rtl/verilog/Clk_ctrl.v
./trunk/rtl/verilog/MAC_rx.v
./trunk/rtl/verilog/MAC_tx/
./trunk/rtl/verilog/MAC_tx/flow_ctrl.v
./trunk/rtl/verilog/MAC_tx/MAC_tx_addr_add.v
./trunk/rtl/verilog/MAC_tx/MAC_tx_Ctrl.v
./trunk/rtl/verilog/MAC_tx/MAC_tx_FF.v
./trunk/rtl/verilog/MAC_tx/Ramdon_gen.v
./trunk/rtl/verilog/MAC_tx/CRC_gen.v
./trunk/rtl/verilog/reg_int.v
./trunk/syn/
./trunk/syn/syn_altrea.prj
./trunk/syn/syn_xilinx.prj
./trunk/syn/syn.prj
./trunk/sim/
./trunk/sim/rtl_sim/
./trunk/sim/rtl_sim/modsim_sim/
./trunk/sim/rtl_sim/modsim_sim/data/
./trunk/sim/rtl_sim/modsim_sim/data/10Mbps_duplex.vec
./trunk/sim/rtl_sim/modsim_sim/data/46-80.ini
./trunk/sim/rtl_sim/modsim_sim/data/target_mac_check.vec
./trunk/sim/rtl_sim/modsim_sim/data/1000Mbps_duplex.vec
./trunk/sim/rtl_sim/modsim_sim/data/CPU.vec
./trunk/sim/rtl_sim/modsim_sim/data/46-46.ini
./trunk/sim/rtl_sim/modsim_sim/data/flow_ctrl.vec
./trunk/sim/rtl_sim/modsim_sim/data/46-100.ini
./trunk/sim/rtl_sim/modsim_sim/data/source_mac_replace.vec
./trunk/sim/rtl_sim/modsim_sim/data/batch.dat
./trunk/sim/rtl_sim/modsim_sim/data/48-48.ini
./trunk/sim/rtl_sim/modsim_sim/data/47-47.ini
./trunk/sim/rtl_sim/modsim_sim/data/100Mbps_duplex.vec
./trunk/sim/rtl_sim/modsim_sim/data/config.ini
./trunk/sim/rtl_sim/modsim_sim/data/46-50.ini
./trunk/sim/rtl_sim/modsim_sim/bin/
./trunk/sim/rtl_sim/modsim_sim/bin/sim.mod
./trunk/sim/rtl_sim/modsim_sim/bin/ip_32W_check.dll
./trunk/sim/rtl_sim/modsim_sim/bin/vlog-rtl.list
./trunk/sim/rtl_sim/modsim_sim/bin/com.mod
./trunk/sim/rtl_sim/modsim_sim/bin/sim_only.mod
./trunk/sim/rtl_sim/modsim_sim/bin/ip_32W_gen.dll
./trunk/sim/rtl_sim/modsim_sim/script/
./trunk/sim/rtl_sim/modsim_sim/script/set_stimulus.tcl
./trunk/sim/rtl_sim/modsim_sim/script/batch_mode.tcl
./trunk/sim/rtl_sim/modsim_sim/script/run.tcl
./trunk/sim/rtl_sim/modsim_sim/script/start_verify.tcl
./trunk/sim/rtl_sim/modsim_sim/script/filesel.tcl
./trunk/sim/rtl_sim/modsim_sim/script/set_reg_data.tcl
./trunk/sim/rtl_sim/modsim_sim/script/run_proc.tcl
./trunk/sim/rtl_sim/modsim_sim/script/user_lib.tcl
./trunk/sim/rtl_sim/modsim_sim/log/
./trunk/sim/rtl_sim/modsim_sim/log/ncsim.log
./trunk/sim/rtl_sim/ncsim_sim/
./trunk/sim/rtl_sim/ncsim_sim/data/
./trunk/sim/rtl_sim/ncsim_sim/data/10Mbps_duplex.vec
./trunk/sim/rtl_sim/ncsim_sim/data/target_mac_check.vec
./trunk/sim/rtl_sim/ncsim_sim/data/1000Mbps_duplex.vec
./trunk/sim/rtl_sim/ncsim_sim/data/CPU.vec
./trunk/sim/rtl_sim/ncsim_sim/data/flow_ctrl.vec
./trunk/sim/rtl_sim/ncsim_sim/data/source_mac_replace.vec
./trunk/sim/rtl_sim/ncsim_sim/data/batch.dat
./trunk/sim/rtl_sim/ncsim_sim/data/100Mbps_duplex.vec
./trunk/sim/rtl_sim/ncsim_sim/data/config.ini
./trunk/sim/rtl_sim/ncsim_sim/data/46-50.ini
./trunk/sim/rtl_sim/ncsim_sim/bin/
./trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_check_vpi.dll
./trunk/sim/rtl_sim/ncsim_sim/bin/sim.nc
./trunk/sim/rtl_sim/ncsim_sim/bin/com.nc
./trunk/sim/rtl_sim/ncsim_sim/bin/sim_only.nc
./trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_check.dll
./trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_gen_vpi.dll
./trunk/sim/rtl_sim/ncsim_sim/bin/vlog.list
./trunk/sim/rtl_sim/ncsim_sim/bin/cds.lib
./trunk/sim/rtl_sim/ncsim_sim/bin/config.ini
./trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_gen.dll
./trunk/sim/rtl_sim/ncsim_sim/bin/hdl.var
./trunk/sim/rtl_sim/ncsim_sim/script/
./trunk/sim/rtl_sim/ncsim_sim/script/set_stimulus.tcl
./trunk/sim/rtl_sim/ncsim_sim/script/batch_mode.tcl
./trunk/sim/rtl_sim/ncsim_sim/script/run.tcl
./trunk/sim/rtl_sim/ncsim_sim/script/start_verify.tcl
./trunk/sim/rtl_sim/ncsim_sim/script/filesel.tcl
./trunk/sim/rtl_sim/ncsim_sim/script
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