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gh_timer_8254_081608
- Timer 8254 Verilog source code
pit_latest.tar
- Programmable Interval Timer: Overview Category :: Other Language :: Verilog Development status :: Beta WishBone Compliant :: Yes Phazes :: Design done, Specification done
StopWatch
- 用C#写的跑表，用于学习Timer控件和C#下的stopwatch类，在VS.net 2005下运行通过.-Using C# to write the stopwatch for the study and Timer controls and C# under the stopwatch class, VS.net 2005 in the run through.
verilog
- verilog code for a microwave controller with clock output, clock time setting input, power control input+output, cooking timer setup, door open light, cooking complete buzzer output. Four push buttons provide following active low input signal
LIP1701CORE_system_watchdog
- System watchdog verilog code
Timer
- 用verilog语言实现的定时器。在DE2-70开发板上设计，七段数码管分别用于显示时/分/秒，并带有预置时间功能。-Timer verilog language. DE2-70 development board design, seven-segment digital tubes were used to display hours/minutes/seconds, with the function of the preset time.
digital_clock
- QUARTUS中实现数字钟，有计时计分计秒的功能，整点报时的功能，用VERILOG实现。-QUARTUS achieve digital clock, a timer function scoring the seconds, the whole point timekeeping function, using VERILOG implementation.
pwm.tar
- PWM Timer Verilog Design
lan
- 基于Verilog的篮球计时器，可以实现正常篮球比赛所需的各种功能-Basketball timer
univ_TIMER
- verilog source code of programable timer
StopWatch
- verilog实现数字式秒表，秒表有一个按键开关：当电路处于“初始”状态时，第一次按键，计时开始（“计时”状态）；再 次按键。计时停止（“停止”状态）；第三次按键，计时器复位为 0’0’.0’’，且电路恢复到“初始”状态。详见压缩文件包内pdf说明。-Verilog in implementing digital stopwatch, stopwatches have a key switch: when the circuit is in the initial State, firs
apb_timer
- Verilog code of timer for APB
miaobiao7
- 秒表计数（verilog）可以实现百分秒，秒，分的计数60进制，可以暂停，复位(Stopwatch count (Verilog) can achieve 100 seconds, seconds, the count is 60 hexadecimal, you can pause, reset)
module clock
- 一款运动计时器的设计，包含了时、分、秒的设计。(The design of a sports timer includes hour, minute and second designs.)
071162程序
- 设计一个用于篮球比赛的定时器。要求： （1）定时时间为24秒，按递减方式计时，每隔1秒，定时器减1； （2）定时器的时间用两位数码管显示； （3）设置两个外部控制开关，开关K1控制定时器的直接复位/启动计时，开关K2控制定时器的暂停/连续计时；当定时器递减计时到零（即定时时间到）时，定时器保持零不变，同时发出报警信号，报警信号用一个发光二极管指示。 （4）输入时钟脉冲的频率为50MHz。 （5）用Verilog HDL语言设计，用Modelsim软件做功能仿真，用Quartus II综