以太网MAC层IP核设计Veriolg代码，包括TESTBECH平台和设计文档-Ethernet MAC layer IP core design Veriolg code, including TESTBECH platform and design documents

10/100 0M以太网MAC解决方案，是IP核的相关说明，利用ALTERA的FPGA设计，QUARTUS软件为开发平台。-10/100/1000M Ethernet MAC solution is the IP core instructions, using ALTERA' s FPGA design, QUARTUS software development platform.

这是去年我编写的基于xilinx FPGA的MAC IP 核开发的驱动DM9000的源代码。基于Verilog 语言。-This is the last year I wrote based on xilinx FPGA the MAC IP core developed DM9000 driver source code. Based Verilog language.