Verilog语言开发环境ISE例程，适合于初学者-ISE Verilog language development environment routines, suitable for beginners

码表程序，完整的verilog工程文件，完整的工程设计流程，包含时序约束，ip核的嵌入，以及DCM模块的使用-Stopwatch program, complete verilog project file, complete engineering design process, including the timing constraints, ip nuclear embedding, as well as the use of DCM module