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文件名称:VHDLmipsPipeline

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  • 上传时间:
    2012-11-16
  • 文件大小:
    548.33kb
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    0次
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32 位MIP流水线CPU设计,5 stage,代码详细,包括ALU,存储器,寄存器等,是个很不错的CPU设计-32 MIP pipelined CPU design, 5 stage, the code in detail, including the ALU, memory, registers, etc. is a very good CPU design
(系统自动生成,下载前可以参看下载内容)

下载文件列表

mips_Pipeline/.recordref
mips_Pipeline/afg.jhd
mips_Pipeline/afg.tbw
mips_Pipeline/afg.udo
mips_Pipeline/afg.xwv
mips_Pipeline/afg.xwv_bak
mips_Pipeline/alu.prj
mips_Pipeline/alu.vhd
mips_Pipeline/alu_control.vhd
mips_Pipeline/alu_vhdl.prj
mips_Pipeline/asde.xwv
mips_Pipeline/asde.xwv_bak
mips_Pipeline/asdf.jhd
mips_Pipeline/asdf.tbw
mips_Pipeline/asdf.udo
mips_Pipeline/asdf.xwv
mips_Pipeline/asdf.xwv_bak
mips_Pipeline/automake.log
mips_Pipeline/control.vhd
mips_Pipeline/datapath.edn
mips_Pipeline/datapath.fse
mips_Pipeline/datapath.ncf
mips_Pipeline/datapath.prj
mips_Pipeline/datapath.sdc
mips_Pipeline/datapath.srd
mips_Pipeline/datapath.srm
mips_Pipeline/datapath.srr
mips_Pipeline/datapath.srs
mips_Pipeline/datapath.tbw
mips_Pipeline/datapath.vhd
mips_Pipeline/datapath.xwv
mips_Pipeline/datapath.xwv_bak
mips_Pipeline/datapath_compile.tcl
mips_Pipeline/datapath_map.tcl
mips_Pipeline/layer0.sro
mips_Pipeline/layer0.tlg
mips_Pipeline/mips_core.vhd
mips_Pipeline/mips_ram.vhd
mips_Pipeline/mips_rom.vhd
mips_Pipeline/mips_top.fse
mips_Pipeline/mips_top.ncf
mips_Pipeline/mips_top.prj
mips_Pipeline/mips_top.sdc
mips_Pipeline/mips_top.srd
mips_Pipeline/mips_top.srm
mips_Pipeline/mips_top.srr
mips_Pipeline/mips_top.srs
mips_Pipeline/mips_top.vhd
mips_Pipeline/mips_top_compile.tcl
mips_Pipeline/mips_top_map.tcl
mips_Pipeline/mips_top_summary.html
mips_Pipeline/mips_top_vhdl.prj
mips_Pipeline/newmips2.dhp
mips_Pipeline/newmips2.ise
mips_Pipeline/newmips2.ise_ISE_Backup
mips_Pipeline/pepExtractor.prj
mips_Pipeline/prjname.lso
mips_Pipeline/regestfile.vhd
mips_Pipeline/reg_t.jhd
mips_Pipeline/reg_t.tbw
mips_Pipeline/reg_t.udo
mips_Pipeline/reg_t.xwv
mips_Pipeline/reg_t.xwv_bak
mips_Pipeline/results.txt
mips_Pipeline/rpt_datapath.areasrr
mips_Pipeline/rpt_datapath_areasrr.htm
mips_Pipeline/rpt_mips_top.areasrr
mips_Pipeline/rpt_mips_top_areasrr.htm
mips_Pipeline/stderr.log
mips_Pipeline/stdout.log
mips_Pipeline/syntmp/datapath.msg
mips_Pipeline/syntmp/datapath.plg
mips_Pipeline/syntmp/mips_top.msg
mips_Pipeline/syntmp/mips_top.plg
mips_Pipeline/transcript
mips_Pipeline/traplog.tlg
mips_Pipeline/userlang.tpl
mips_Pipeline/verif/datapath.vif
mips_Pipeline/verif/mips_top.vif
mips_Pipeline/xst/work/hdllib.ref
mips_Pipeline/xst/work/hdpdeps.ref
mips_Pipeline/xst/work/sub00/vhpl00.vho
mips_Pipeline/xst/work/sub00/vhpl01.vho
mips_Pipeline/xst/work/sub00/vhpl02.vho
mips_Pipeline/xst/work/sub00/vhpl03.vho
mips_Pipeline/xst/work/sub00/vhpl04.vho
mips_Pipeline/xst/work/sub00/vhpl05.vho
mips_Pipeline/xst/work/sub00/vhpl06.vho
mips_Pipeline/xst/work/sub00/vhpl07.vho
mips_Pipeline/xst/work/sub00/vhpl08.vho
mips_Pipeline/xst/work/sub00/vhpl09.vho
mips_Pipeline/xst/work/sub00/vhpl10.vho
mips_Pipeline/xst/work/sub00/vhpl11.vho
mips_Pipeline/xst/work/sub00/vhpl12.vho
mips_Pipeline/xst/work/sub00/vhpl13.vho
mips_Pipeline/xst/work/sub00/vhpl14.vho
mips_Pipeline/xst/work/sub00/vhpl15.vho
mips_Pipeline/xst/work/sub00/vhpl16.vho
mips_Pipeline/xst/work/sub00/vhpl17.vho
mips_Pipeline/xst/work/sub00/vhpl18.vho
mips_Pipeline/xst/work/sub00/vhpl19.vho
mips_Pipeline/xst/work/sub00/vhpl20.vho
mips_Pipeline/_mh_info
mips_Pipeline/_verilog_hintfile
mips_Pipeline/__projnav/alu.xst
mips_Pipeline/__projnav/control.xst
mips_Pipeline/__projnav/datapath.ise_created
mips_Pipeline/__projnav/mips_ram.xst
mips_Pipeline/__projnav/mips_rom.xst
mips_Pipeline/__projnav/mips_top.ise_created
mips_Pipeline/__projnav/mips_top.xst
mips_Pipeline/__projnav/newmips2.gfl
mips_Pipeline/__projnav/newmips2_flowplus.gfl
mips_Pipeline/__projnav/runXst_tcl.rsp
mips_Pipeline/__projnav/sumrpt_tcl.rsp
mips_Pipeline/__projnav/xst_sprjTOstx_tcl.rsp
mips_Pipeline/__projnav/__synProj.rsp
mips_Pipeline/__projnav.log
mips_Pipeline/xst/dump.xst/control.prj/ngx/notopt
mips_Pipeline/xst/dump.xst/control.prj/ngx/opt
mips_Pipeline/xst/dump.xst/mips_ram.prj/ngx/notopt
mips_Pipeline/xst/dump.xst/mips_ram.prj/ngx/opt
mips_Pipeline/xst/dump.xst/mips_rom.prj/ngx/notopt
mips_Pipeline/xst/dump.xst/mips_rom.prj/ngx/opt
mips_Pipeline/xst/dump.xst/mips_top.prj/ngx/notopt
mips_Pipeline/xst/dump.xst/mips_top.prj/ngx/opt
mips_Pipeline/xst/dump.xst/control.prj/ngx
mips_Pipeline/xst/dump.xst/mips_ram.prj/ngx
mips_Pipeline/xst/dump.xst/mips_rom.prj/ngx
mips_Pipeline/xst/dump.xst/mips_top.prj/ngx
mips_Pipeline/xst/dump.xst/control.prj
mips_Pipeline/xst/dump.xst/mips_ram.prj
mips_Pipeline/xst/dump.xst/mips_rom.prj
mips_Pipeline/xst/dump.xst/mips_top.prj
mips_Pipeline/xst/work/sub00
mips_Pipeline/xst/dump.xst
mips_Pipeline/xst/work
mips_Pipeline/syntmp
mips_Pipeline/verif
mips_Pipeline/xst
mips_Pipeline/_xmsgs
mips_Pipeline/__projnav
mips_Pipeline

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