文件名称:UART_Verilog
-
所属分类:
- 标签属性:
- 上传时间:2012-11-16
-
文件大小:483.67kb
-
已下载:0次
-
提 供 者:
-
相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
Altera FPGA的UART通讯程序-Altera FPGA' s UART communication program
相关搜索: uart altera
(系统自动生成,下载前可以参看下载内容)
下载文件列表
uart_tb.v.bak
uart_tb.vcd
vsim.wlf
rtl_wrk/@rx/verilog.asm
rtl_wrk/@rx/_primary.dat
rtl_wrk/@rx/_primary.vhd
rtl_wrk/@tx/verilog.asm
rtl_wrk/@tx/_primary.dat
rtl_wrk/@tx/_primary.vhd
rtl_wrk/uart_tb/verilog.asm
rtl_wrk/uart_tb/_primary.dat
rtl_wrk/uart_tb/_primary.vhd
rtl_wrk/_info
modelsim.ini
run.do
Rx.v
Rx.v.bak
Tx.v
Tx.v.bak
uart_tb.v
rtl_wrk/@rx
rtl_wrk/@tx
rtl_wrk/uart_tb
rtl_wrk
uart_tb.vcd
vsim.wlf
rtl_wrk/@rx/verilog.asm
rtl_wrk/@rx/_primary.dat
rtl_wrk/@rx/_primary.vhd
rtl_wrk/@tx/verilog.asm
rtl_wrk/@tx/_primary.dat
rtl_wrk/@tx/_primary.vhd
rtl_wrk/uart_tb/verilog.asm
rtl_wrk/uart_tb/_primary.dat
rtl_wrk/uart_tb/_primary.vhd
rtl_wrk/_info
modelsim.ini
run.do
Rx.v
Rx.v.bak
Tx.v
Tx.v.bak
uart_tb.v
rtl_wrk/@rx
rtl_wrk/@tx
rtl_wrk/uart_tb
rtl_wrk
本网站为编程资源及源代码搜集、介绍的搜索网站,版权归原作者所有! 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.