XDSP/
XDSP/lab4/
XDSP/lab4/aspec_cspec1.m
XDSP/lab4/bandpass_filter.bak
XDSP/lab4/bandpass_filter.mdl
XDSP/lab4/coef.m
XDSP/lab4/interpolatedFIR.fda
XDSP/lab4/interpolatedFIR.mdl
XDSP/lab4/interpolatedfir_interpolated_fir.mrp
XDSP/lab4/interpolatedfir_normal_fir.mrp
XDSP/lab4/lab4_soln/
XDSP/lab4/lab4_soln/aspec_cspec1.m
XDSP/lab4/lab4_soln/bandpass_filter.mdl
XDSP/lab4/lab4_soln/bandpass_filter_config.m
XDSP/lab4/lab4_soln/bandpass_filter_hwcosim.mdl
XDSP/lab4/lab4_soln/bandpass_filter_hwcosim_config.m
XDSP/lab4/lab4_soln/bandpass_filter_hwcosim_hwcosim_lib.mdl
XDSP/lab4/lab4_soln/board/
XDSP/lab4/lab4_soln/board/automake.log
XDSP/lab4/lab4_soln/board/bandpass_filter_hwcosim.vhd
XDSP/lab4/lab4_soln/board/bandpass_filter_hwcosim_clk_wrapper.bit
XDSP/lab4/lab4_soln/board/bandpass_filter_hwcosim_clk_wrapper.dhp
XDSP/lab4/lab4_soln/board/bandpass_filter_hwcosim_clk_wrapper.npl
XDSP/lab4/lab4_soln/board/bandpass_filter_hwcosim_clk_wrapper.vhd
XDSP/lab4/lab4_soln/board/bandpass_filter_hwcosim_clk_wrapper.xcf
XDSP/lab4/lab4_soln/board/bandpass_filter_hwcosim_clk_wrapper_config.cmd
XDSP/lab4/lab4_soln/board/bandpass_filter_hwcosim_clk_wrapper_config.log
XDSP/lab4/lab4_soln/board/bandpass_filter_hwcosim_clock_driver.vhd
XDSP/lab4/lab4_soln/board/bandpass_filter_hwcosim_config.m
XDSP/lab4/lab4_soln/board/bandpass_filter_hwcosim_dcm_wrapper.vhd
XDSP/lab4/lab4_soln/board/bandpass_filter_hwcosim_FIR.coe
XDSP/lab4/lab4_soln/board/bandpass_filter_hwcosim_FIR.mif
XDSP/lab4/lab4_soln/board/bandpass_filter_hwcosim_fir.vhd
XDSP/lab4/lab4_soln/board/bandpass_filter_hwcosim_hwcosim_lib.mdl
XDSP/lab4/lab4_soln/board/clkwrapperinterface
XDSP/lab4/lab4_soln/board/clkwrapperinterface.txt
XDSP/lab4/lab4_soln/board/clock_pkg.vhd
XDSP/lab4/lab4_soln/board/conv_pkg.vhd
XDSP/lab4/lab4_soln/board/coregen_tmp/
XDSP/lab4/lab4_soln/board/coregen_tmp/distributed_arithmetic_fir_filter_spartan2_8_0_b0cf4f8b28bc6b9e.edn
XDSP/lab4/lab4_soln/board/coregen_tmp/distributed_arithmetic_fir_filter_spartan2_8_0_b0cf4f8b28bc6b9e.mif
XDSP/lab4/lab4_soln/board/coregen_tmp/distributed_arithmetic_fir_filter_spartan2_8_0_b0cf4f8b28bc6b9e.v
XDSP/lab4/lab4_soln/board/coregen_tmp/distributed_arithmetic_fir_filter_spartan2_8_0_b0cf4f8b28bc6b9e.veo
XDSP/lab4/lab4_soln/board/coregen_tmp/distributed_arithmetic_fir_filter_spartan2_8_0_b0cf4f8b28bc6b9e.xco
XDSP/lab4/lab4_soln/board/coregen_tmp/distributed_arithmetic_fir_filter_spartan2_8_0_b0cf4f8b28bc6b9e.xcp
XDSP/lab4/lab4_soln/board/coregen_tmp/distributed_arithmetic_fir_filter_spartan2_8_0_b0cf4f8b28bc6b9e_flist.txt
XDSP/lab4/lab4_soln/board/dcmwrapperinterface
XDSP/lab4/lab4_soln/board/distributed_arithmetic_fir_filter_spartan2_8_0_b0cf4f8b28bc6b9e.edn
XDSP/lab4/lab4_soln/board/globals
XDSP/lab4/lab4_soln/board/jtagcosim_top.ucf
XDSP/lab4/lab4_soln/board/jtagcosim_top.vhd
XDSP/lab4/lab4_soln/board/postnetlist.log
XDSP/lab4/lab4_soln/board/sync_fifo.vhd
XDSP/lab4/lab4_soln/board/synth_model/
XDSP/lab4/lab4_soln/board/synth_model/bandpass_filter_hwcosim.vhd
XDSP/lab4/lab4_soln/board/synth_model/bandpass_filter_hwcosim_clk_wrapper.lso
XDSP/lab4/lab4_soln/board/synth_model/bandpass_filter_hwcosim_clk_wrapper.ngc
XDSP/lab4/lab4_soln/board/synth_model/bandpass_filter_hwcosim_clk_wrapper.results
XDSP/lab4/lab4_soln/board/synth_model/bandpass_filter_hwcosim_clk_wrapper.vhd
XDSP/lab4/lab4_soln/board/synth_model/bandpass_filter_hwcosim_clk_wrapper.xcf
XDSP/lab4/lab4_soln/board/synth_model/bandpass_filter_hwcosim_clock_driver.vhd
XDSP/lab4/lab4_soln/board/synth_model/bandpass_filter_hwcosim_fir.vhd
XDSP/lab4/lab4_soln/board/synth_model/clock_pkg.vhd
XDSP/lab4/lab4_soln/board/synth_model/commandLines
XDSP/lab4/lab4_soln/board/synth_model/conv_pkg.vhd
XDSP/lab4/lab4_soln/board/synth_model/distributed_arithmetic_fir_filter_spartan2_8_0_b0cf4f8b28bc6b9e.edn
XDSP/lab4/lab4_soln/board/synth_model/distributed_arithmetic_fir_filter_spartan2_8_0_b0cf4f8b28bc6b9e.ngo
XDSP/lab4/lab4_soln/board/synth_model/sync_fifo.vhd
XDSP/lab4/lab4_soln/board/synth_model/synth_reg.vhd
XDSP/lab4/lab4_soln/board/synth_model/synth_reg_w_init.vhd
XDSP/lab4/lab4_soln/board/synth_model/vhdlFiles
XDSP/lab4/lab4_soln/board/synth_model/xlclkprobe.vhd
XDSP/lab4/lab4_soln/board/synth_model/xlclockdriver.vhd
XDSP/lab4/lab4_soln/board/synth_model/xlclockgenerator.vhd
XDSP/lab4/lab4_soln/board/synth_model/xlconvert.vhd
XDSP/lab4/lab4_soln/board/synth_model/xldelay.vhd
XDSP/lab4/lab4_soln/board/synth_model/xlsl2slv.vhd
XDSP/lab4/lab4_soln/board/synth_model/xlslv2sl.vhd
XDSP/lab4/lab4_soln/board/synth_model/xst/
XDSP/lab4/lab4_soln/board/synth_model/xst/work/
XDSP/lab4/lab4_soln/board/synth_model/xst/work/hdllib.ref
XDSP/lab4/lab4_soln/board/synth_model/xst/work/hdpdeps.ref
XDSP/lab4/lab4_soln/board/synth_model/xst/work/sub00/
XDSP/lab4/lab4_soln/board/synth_model/xst/work/sub00/vhpl00.vho
XDSP/lab4/lab4_soln/board/synth_model/xst/work/sub00/vhpl01.vho
XDSP/lab4/lab4_soln/board/synth_model/xst/work/sub00/vhpl02.vho
XDSP/lab4/lab4_soln/board/synth_model/xst/work/sub00/vhpl03.vho
XDSP/lab4/lab4_soln/board/synth_model/xst/work/sub00/vhpl04.vho
XDSP/lab4/lab4_soln/board/synth_model/xs