文件名称:VHDLchengfaqi
-
所属分类:
- 标签属性:
- 上传时间:2012-11-16
-
文件大小:1.37mb
-
已下载:0次
-
提 供 者:
-
相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
基于verilog+HDL实现的恒定乘法器设计,里面有详细的源码。-Verilog+ HDL-based implementation of the constant multiplier design, which has detailed source.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
恒定系数乘法器实验/
恒定系数乘法器实验/Project/
恒定系数乘法器实验/Project/multiply/
恒定系数乘法器实验/Project/multiply/component/
恒定系数乘法器实验/Project/multiply/constraint/
恒定系数乘法器实验/Project/multiply/constraint/multiply.pdc
恒定系数乘法器实验/Project/multiply/constraint/multiply_1.pdc
恒定系数乘法器实验/Project/multiply/coreconsole/
恒定系数乘法器实验/Project/multiply/designer/
恒定系数乘法器实验/Project/multiply/designer/impl1/
恒定系数乘法器实验/Project/multiply/designer/impl1/designer.log
恒定系数乘法器实验/Project/multiply/designer/impl1/designer_gen_ba.log
恒定系数乘法器实验/Project/multiply/designer/impl1/multiply.adb
恒定系数乘法器实验/Project/multiply/designer/impl1/multiply.dtf/
恒定系数乘法器实验/Project/multiply/designer/impl1/multiply.dtf/verify.log
恒定系数乘法器实验/Project/multiply/designer/impl1/multiply.ide_des
恒定系数乘法器实验/Project/multiply/designer/impl1/multiply.lok
恒定系数乘法器实验/Project/multiply/designer/impl1/multiply.pdb
恒定系数乘法器实验/Project/multiply/designer/impl1/multiply.pdb.depends
恒定系数乘法器实验/Project/multiply/designer/impl1/multiply.stp
恒定系数乘法器实验/Project/multiply/designer/impl1/multiply.tcl
恒定系数乘法器实验/Project/multiply/designer/impl1/multiply_ba.sdf
恒定系数乘法器实验/Project/multiply/designer/impl1/multiply_ba.v
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/multiply/
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/multiply/verilog.psm
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/multiply/_primary.dat
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/multiply/_primary.vhd
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/stimulus/
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/stimulus/verilog.psm
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/stimulus/_primary.dat
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/stimulus/_primary.vhd
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/tb_clock_minmax/
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/tb_clock_minmax/verilog.psm
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/tb_clock_minmax/_primary.dat
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/tb_clock_minmax/_primary.vhd
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/testbench/
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/testbench/verilog.psm
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/testbench/_primary.dat
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/testbench/_primary.vhd
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/_info
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/_temp/
恒定系数乘法器实验/Project/multiply/hdl/
恒定系数乘法器实验/Project/multiply/hdl/hdlsynchk.tcl
恒定系数乘法器实验/Project/multiply/hdl/loader.v
恒定系数乘法器实验/Project/multiply/hdl/multiplier.v
恒定系数乘法器实验/Project/multiply/hdl/multiply.v
恒定系数乘法器实验/Project/multiply/hdl/waveperl.log
恒定系数乘法器实验/Project/multiply/multiply.prj
恒定系数乘法器实验/Project/multiply/phy_synthesis/
恒定系数乘法器实验/Project/multiply/simulation/
恒定系数乘法器实验/Project/multiply/simulation/meminit.dat
恒定系数乘法器实验/Project/multiply/simulation/modelsim.ini
恒定系数乘法器实验/Project/multiply/simulation/modelsim.ini.sav
恒定系数乘法器实验/Project/multiply/simulation/modelsim.log
恒定系数乘法器实验/Project/multiply/simulation/presynth/
恒定系数乘法器实验/Project/multiply/simulation/presynth/@p@l@l_1@m/
恒定系数乘法器实验/Project/multiply/simulation/presynth/@p@l@l_1@m/verilog.psm
恒定系数乘法器实验/Project/multiply/simulation/presynth/@p@l@l_1@m/_primary.dat
恒定系数乘法器实验/Project/multiply/simulation/presynth/@p@l@l_1@m/_primary.vhd
恒定系数乘法器实验/Project/multiply/simulation/presynth/loader/
恒定系数乘法器实验/Project/multiply/simulation/presynth/loader/verilog.psm
恒定系数乘法器实验/Project/multiply/simulation/presynth/loader/_primary.dat
恒定系数乘法器实验/Project/multiply/simulation/presynth/loader/_primary.vhd
恒定系数乘法器实验/Project/multiply/simulation/presynth/multiplier/
恒定系数乘法器实验/Project/multiply/simulation/presynth/multiplier/verilog.psm
恒定系数乘法器实验/Project/multiply/simulation/presynth/multiplier/_primary.dat
恒定系数乘法器实验/Project/multiply/simulation/presynth/multiplier/_primary.vhd
恒定系数乘法器实验/Project/multiply/simulation/presynth/multiply/
恒定系数乘法器实验/Project/multiply/simulation/presynth/multiply/verilog.psm
恒定系数乘法器实验/Project/multiply/simulation/presynth/multiply/_primary.dat
恒定系数乘法器实验/Project/multiply/simulation/presynth/multiply/_primary.vhd
恒定系数乘法器实验/Project/multiply/simulation/presynth/ram16x8/
恒定系数乘法器实验/Project/multiply/simulation/presynth/ram16x8/verilog.psm
恒定系数乘法器实验/Project/multiply/simulation/presynth/ram16x8/_primary.dat
恒定系数乘法器实验/Project/multiply/simulation/presynth/ram16x8/_primary.vhd
恒定系数乘法器实验/Project/multiply/simulation/presynth/stimulus/
恒定系数乘法器实验/Project/multiply/simulation/presynth/stimulus/verilog.psm
恒定系数乘法器实验/Project/multiply/simulation/presynth/stimulus/_primary.dat
恒定系数乘法器实验/Project/multiply/simulation/presynth/stimulus/_primary.vhd
恒定系数乘法器实验/Project/multiply/simulation/presynth/tb_clock_minmax/
恒定系数乘法器实验/Project/multiply/simulation/presynth/tb_clock_minmax/verilog.psm
恒定系数乘法器实验/Project/multiply/simulation/presynth/tb_c
恒定系数乘法器实验/Project/
恒定系数乘法器实验/Project/multiply/
恒定系数乘法器实验/Project/multiply/component/
恒定系数乘法器实验/Project/multiply/constraint/
恒定系数乘法器实验/Project/multiply/constraint/multiply.pdc
恒定系数乘法器实验/Project/multiply/constraint/multiply_1.pdc
恒定系数乘法器实验/Project/multiply/coreconsole/
恒定系数乘法器实验/Project/multiply/designer/
恒定系数乘法器实验/Project/multiply/designer/impl1/
恒定系数乘法器实验/Project/multiply/designer/impl1/designer.log
恒定系数乘法器实验/Project/multiply/designer/impl1/designer_gen_ba.log
恒定系数乘法器实验/Project/multiply/designer/impl1/multiply.adb
恒定系数乘法器实验/Project/multiply/designer/impl1/multiply.dtf/
恒定系数乘法器实验/Project/multiply/designer/impl1/multiply.dtf/verify.log
恒定系数乘法器实验/Project/multiply/designer/impl1/multiply.ide_des
恒定系数乘法器实验/Project/multiply/designer/impl1/multiply.lok
恒定系数乘法器实验/Project/multiply/designer/impl1/multiply.pdb
恒定系数乘法器实验/Project/multiply/designer/impl1/multiply.pdb.depends
恒定系数乘法器实验/Project/multiply/designer/impl1/multiply.stp
恒定系数乘法器实验/Project/multiply/designer/impl1/multiply.tcl
恒定系数乘法器实验/Project/multiply/designer/impl1/multiply_ba.sdf
恒定系数乘法器实验/Project/multiply/designer/impl1/multiply_ba.v
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/multiply/
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/multiply/verilog.psm
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/multiply/_primary.dat
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/multiply/_primary.vhd
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/stimulus/
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/stimulus/verilog.psm
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/stimulus/_primary.dat
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/stimulus/_primary.vhd
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/tb_clock_minmax/
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/tb_clock_minmax/verilog.psm
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/tb_clock_minmax/_primary.dat
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/tb_clock_minmax/_primary.vhd
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/testbench/
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/testbench/verilog.psm
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/testbench/_primary.dat
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/testbench/_primary.vhd
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/_info
恒定系数乘法器实验/Project/multiply/designer/impl1/simulation/postlayout/_temp/
恒定系数乘法器实验/Project/multiply/hdl/
恒定系数乘法器实验/Project/multiply/hdl/hdlsynchk.tcl
恒定系数乘法器实验/Project/multiply/hdl/loader.v
恒定系数乘法器实验/Project/multiply/hdl/multiplier.v
恒定系数乘法器实验/Project/multiply/hdl/multiply.v
恒定系数乘法器实验/Project/multiply/hdl/waveperl.log
恒定系数乘法器实验/Project/multiply/multiply.prj
恒定系数乘法器实验/Project/multiply/phy_synthesis/
恒定系数乘法器实验/Project/multiply/simulation/
恒定系数乘法器实验/Project/multiply/simulation/meminit.dat
恒定系数乘法器实验/Project/multiply/simulation/modelsim.ini
恒定系数乘法器实验/Project/multiply/simulation/modelsim.ini.sav
恒定系数乘法器实验/Project/multiply/simulation/modelsim.log
恒定系数乘法器实验/Project/multiply/simulation/presynth/
恒定系数乘法器实验/Project/multiply/simulation/presynth/@p@l@l_1@m/
恒定系数乘法器实验/Project/multiply/simulation/presynth/@p@l@l_1@m/verilog.psm
恒定系数乘法器实验/Project/multiply/simulation/presynth/@p@l@l_1@m/_primary.dat
恒定系数乘法器实验/Project/multiply/simulation/presynth/@p@l@l_1@m/_primary.vhd
恒定系数乘法器实验/Project/multiply/simulation/presynth/loader/
恒定系数乘法器实验/Project/multiply/simulation/presynth/loader/verilog.psm
恒定系数乘法器实验/Project/multiply/simulation/presynth/loader/_primary.dat
恒定系数乘法器实验/Project/multiply/simulation/presynth/loader/_primary.vhd
恒定系数乘法器实验/Project/multiply/simulation/presynth/multiplier/
恒定系数乘法器实验/Project/multiply/simulation/presynth/multiplier/verilog.psm
恒定系数乘法器实验/Project/multiply/simulation/presynth/multiplier/_primary.dat
恒定系数乘法器实验/Project/multiply/simulation/presynth/multiplier/_primary.vhd
恒定系数乘法器实验/Project/multiply/simulation/presynth/multiply/
恒定系数乘法器实验/Project/multiply/simulation/presynth/multiply/verilog.psm
恒定系数乘法器实验/Project/multiply/simulation/presynth/multiply/_primary.dat
恒定系数乘法器实验/Project/multiply/simulation/presynth/multiply/_primary.vhd
恒定系数乘法器实验/Project/multiply/simulation/presynth/ram16x8/
恒定系数乘法器实验/Project/multiply/simulation/presynth/ram16x8/verilog.psm
恒定系数乘法器实验/Project/multiply/simulation/presynth/ram16x8/_primary.dat
恒定系数乘法器实验/Project/multiply/simulation/presynth/ram16x8/_primary.vhd
恒定系数乘法器实验/Project/multiply/simulation/presynth/stimulus/
恒定系数乘法器实验/Project/multiply/simulation/presynth/stimulus/verilog.psm
恒定系数乘法器实验/Project/multiply/simulation/presynth/stimulus/_primary.dat
恒定系数乘法器实验/Project/multiply/simulation/presynth/stimulus/_primary.vhd
恒定系数乘法器实验/Project/multiply/simulation/presynth/tb_clock_minmax/
恒定系数乘法器实验/Project/multiply/simulation/presynth/tb_clock_minmax/verilog.psm
恒定系数乘法器实验/Project/multiply/simulation/presynth/tb_c
本网站为编程资源及源代码搜集、介绍的搜索网站,版权归原作者所有! 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.