文件名称:VHDL_Development_Board_Sources
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这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟.-which I have recently bought a CPLD Development Board VHDL source code accompanied the development of the plate diagram, You hope to be a good help! which states : eight priority encoder, multipliers, multi-path selectors, BCD binary switch, adder, subtraction device, the simple state machine, four comparators, seven of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng, traffic lights, Digital Clock.
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下载文件列表
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.asm.rpt
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.bdf
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.cdf
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.done
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.fit.eqn
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.fit.rpt
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.fit.summary
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.flow.rpt
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.map.eqn
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.map.rpt
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.map.summary
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.pin
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.pof
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.qpf
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.qsf
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.qws
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.tan.rpt
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.tan.summary
VHDL_Development_Board_Sources/综合实验/数字时钟/clock_assignment_defaults.qdf
VHDL_Development_Board_Sources/综合实验/数字时钟/cmp_state.ini
VHDL_Development_Board_Sources/综合实验/数字时钟/decode47.bsf
VHDL_Development_Board_Sources/综合实验/数字时钟/decode47.vhd
VHDL_Development_Board_Sources/综合实验/数字时钟/fen1.bsf
VHDL_Development_Board_Sources/综合实验/数字时钟/fen1.vhd
VHDL_Development_Board_Sources/综合实验/数字时钟/fen100.bsf
VHDL_Development_Board_Sources/综合实验/数字时钟/fen100.vhd
VHDL_Development_Board_Sources/综合实验/数字时钟/fen24.bsf
VHDL_Development_Board_Sources/综合实验/数字时钟/fen24.vhd
VHDL_Development_Board_Sources/综合实验/数字时钟/fen60.bsf
VHDL_Development_Board_Sources/综合实验/数字时钟/fen60.vhd
VHDL_Development_Board_Sources/综合实验/数字时钟/lpm_counter0.bsf
VHDL_Development_Board_Sources/综合实验/数字时钟/lpm_counter0.cmp
VHDL_Development_Board_Sources/综合实验/数字时钟/lpm_counter0.vhd
VHDL_Development_Board_Sources/综合实验/数字时钟/lpm_counter0_wave0.jpg
VHDL_Development_Board_Sources/综合实验/数字时钟/lpm_counter0_waveforms.html
VHDL_Development_Board_Sources/综合实验/数字时钟/sel.bsf
VHDL_Development_Board_Sources/综合实验/数字时钟/sel.vhd
VHDL_Development_Board_Sources/综合实验/数字时钟/serv_req_info.txt
VHDL_Development_Board_Sources/综合实验/数字时钟/talkback/clock.asm.talkback.xml
VHDL_Development_Board_Sources/综合实验/数字时钟/talkback/clock.fit.talkback.xml
VHDL_Development_Board_Sources/综合实验/数字时钟/talkback/clock.map.talkback.xml
VHDL_Development_Board_Sources/综合实验/数字时钟/talkback/clock.rpp.talkback.xml
VHDL_Development_Board_Sources/综合实验/数字时钟/talkback/clock.tan.talkback.xml
VHDL_Development_Board_Sources/综合实验/数字时钟/talkback
VHDL_Development_Board_Sources/综合实验/数字时钟/db/add_sub_0eh.tdf
VHDL_Development_Board_Sources/综合实验/数字时钟/db/add_sub_9ph.tdf
VHDL_Development_Board_Sources/综合实验/数字时钟/db/add_sub_aph.tdf
VHDL_Development_Board_Sources/综合实验/数字时钟/db/add_sub_bph.tdf
VHDL_Development_Board_Sources/综合实验/数字时钟/db/add_sub_vdh.tdf
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(0).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(0).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(1).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(1).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(10).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(10).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(2).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(2).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(3).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(3).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(4).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(4).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(5).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(5).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(6).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(6).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(7).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(7).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(8).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(8).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(9).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(9).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(0).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(0).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(1).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(1).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(10).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(10).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(11).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(11).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(12).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(12).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(13).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(13).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(14).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(14).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(15).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/d
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.bdf
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.cdf
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.done
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.fit.eqn
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.fit.rpt
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.fit.summary
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.flow.rpt
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.map.eqn
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.map.rpt
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.map.summary
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.pin
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.pof
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.qpf
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.qsf
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.qws
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.tan.rpt
VHDL_Development_Board_Sources/综合实验/数字时钟/clock.tan.summary
VHDL_Development_Board_Sources/综合实验/数字时钟/clock_assignment_defaults.qdf
VHDL_Development_Board_Sources/综合实验/数字时钟/cmp_state.ini
VHDL_Development_Board_Sources/综合实验/数字时钟/decode47.bsf
VHDL_Development_Board_Sources/综合实验/数字时钟/decode47.vhd
VHDL_Development_Board_Sources/综合实验/数字时钟/fen1.bsf
VHDL_Development_Board_Sources/综合实验/数字时钟/fen1.vhd
VHDL_Development_Board_Sources/综合实验/数字时钟/fen100.bsf
VHDL_Development_Board_Sources/综合实验/数字时钟/fen100.vhd
VHDL_Development_Board_Sources/综合实验/数字时钟/fen24.bsf
VHDL_Development_Board_Sources/综合实验/数字时钟/fen24.vhd
VHDL_Development_Board_Sources/综合实验/数字时钟/fen60.bsf
VHDL_Development_Board_Sources/综合实验/数字时钟/fen60.vhd
VHDL_Development_Board_Sources/综合实验/数字时钟/lpm_counter0.bsf
VHDL_Development_Board_Sources/综合实验/数字时钟/lpm_counter0.cmp
VHDL_Development_Board_Sources/综合实验/数字时钟/lpm_counter0.vhd
VHDL_Development_Board_Sources/综合实验/数字时钟/lpm_counter0_wave0.jpg
VHDL_Development_Board_Sources/综合实验/数字时钟/lpm_counter0_waveforms.html
VHDL_Development_Board_Sources/综合实验/数字时钟/sel.bsf
VHDL_Development_Board_Sources/综合实验/数字时钟/sel.vhd
VHDL_Development_Board_Sources/综合实验/数字时钟/serv_req_info.txt
VHDL_Development_Board_Sources/综合实验/数字时钟/talkback/clock.asm.talkback.xml
VHDL_Development_Board_Sources/综合实验/数字时钟/talkback/clock.fit.talkback.xml
VHDL_Development_Board_Sources/综合实验/数字时钟/talkback/clock.map.talkback.xml
VHDL_Development_Board_Sources/综合实验/数字时钟/talkback/clock.rpp.talkback.xml
VHDL_Development_Board_Sources/综合实验/数字时钟/talkback/clock.tan.talkback.xml
VHDL_Development_Board_Sources/综合实验/数字时钟/talkback
VHDL_Development_Board_Sources/综合实验/数字时钟/db/add_sub_0eh.tdf
VHDL_Development_Board_Sources/综合实验/数字时钟/db/add_sub_9ph.tdf
VHDL_Development_Board_Sources/综合实验/数字时钟/db/add_sub_aph.tdf
VHDL_Development_Board_Sources/综合实验/数字时钟/db/add_sub_bph.tdf
VHDL_Development_Board_Sources/综合实验/数字时钟/db/add_sub_vdh.tdf
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(0).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(0).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(1).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(1).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(10).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(10).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(2).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(2).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(3).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(3).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(4).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(4).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(5).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(5).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(6).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(6).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(7).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(7).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(8).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(8).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(9).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock(9).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(0).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(0).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(1).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(1).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(10).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(10).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(11).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(11).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(12).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(12).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(13).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(13).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(14).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(14).cnf.hdb
VHDL_Development_Board_Sources/综合实验/数字时钟/db/clock.(15).cnf.cdb
VHDL_Development_Board_Sources/综合实验/数字时钟/d
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