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文件名称:DualPortRAM

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    1.46mb
  • 已下载：
    0次
  • 提 供 者：
    赵****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

此程序是Verilog HDL语言读写RAM的程序希望大家有用-This is Verilog HDL Promang
相关搜索： hdl

(系统自动生成,下载前可以参看下载内容)

下载文件列表

DualPortRAM/DualPortRAM.prj
DualPortRAM/designer/impl1/ada02592-1.tmp
DualPortRAM/designer/impl1/ada02592-3.tmp
DualPortRAM/designer/impl1/ada02920-3.tmp
DualPortRAM/designer/impl1/ada02920-5.tmp
DualPortRAM/designer/impl1/designer.log
DualPortRAM/designer/impl1/top.ide_des
DualPortRAM/designer/impl1/top.pdb
DualPortRAM/designer/impl1/top.pdb.depends
DualPortRAM/designer/impl1/top.tcl
DualPortRAM/designer/impl1/top_ba.sdf
DualPortRAM/designer/impl1/top_ba.v
DualPortRAM/designer/impl1/top.adb
DualPortRAM/designer/impl1/top.dtf/verify.log
DualPortRAM/designer/impl1/top_fp/$$FlashPro_08873.L$$
DualPortRAM/designer/impl1/top_fp/$$FlashPro_FPBBALTLPT1.L$$
DualPortRAM/designer/impl1/top_fp/top.log
DualPortRAM/designer/impl1/top_fp/top.pro
DualPortRAM/designer/impl1/top_fp/projectData/top.pdb
DualPortRAM/hdl/send.v
DualPortRAM/hdl/top.v
DualPortRAM/hdl/writeram.v
DualPortRAM/hdl/rec.v
DualPortRAM/simulation/RAM2k8_R0C0.mem
DualPortRAM/simulation/RAM2k8_R0C1.mem
DualPortRAM/simulation/RAM2k8_R0C2.mem
DualPortRAM/simulation/RAM2k8_R0C3.mem
DualPortRAM/simulation/modelsim.ini.sav
DualPortRAM/simulation/modelsim.ini
DualPortRAM/smartgen/RAM2k8_work.ixf
DualPortRAM/smartgen/smartgen.aws
DualPortRAM/smartgen/RAM2k8/RAM2k8.cxf
DualPortRAM/smartgen/RAM2k8/RAM2k8.gen
DualPortRAM/smartgen/RAM2k8/RAM2k8.log
DualPortRAM/smartgen/RAM2k8/RAM2k8.shx
DualPortRAM/smartgen/RAM2k8/RAM2k8.v
DualPortRAM/smartgen/RAM2k8/RAM2k8_R0C0.mem
DualPortRAM/smartgen/RAM2k8/RAM2k8_R0C1.mem
DualPortRAM/smartgen/RAM2k8/RAM2k8_R0C2.mem
DualPortRAM/smartgen/RAM2k8/RAM2k8_R0C3.mem
DualPortRAM/synthesis/.recordref
DualPortRAM/synthesis/run_options.txt
DualPortRAM/synthesis/stdout.log
DualPortRAM/synthesis/top.areasrr
DualPortRAM/synthesis/top.edn
DualPortRAM/synthesis/top.map
DualPortRAM/synthesis/top.sdf
DualPortRAM/synthesis/top.so
DualPortRAM/synthesis/top.srd
DualPortRAM/synthesis/top.srm
DualPortRAM/synthesis/top.srr
DualPortRAM/synthesis/top.tlg
DualPortRAM/synthesis/top_sdc.sdc
DualPortRAM/synthesis/traplog.tlg
DualPortRAM/synthesis/top.srs
DualPortRAM/synthesis/top_syn.prj
DualPortRAM/synthesis/backup/top.srr
DualPortRAM/synthesis/syntmp/top.msg
DualPortRAM/synthesis/syntmp/top.plg
DualPortRAM/viewdraw/viewdraw.ini
DualPortRAM/viewdraw/vf/project.lst
DualPortRAM/designer/impl1/top_fp/projectData
DualPortRAM/designer/impl1/simulation
DualPortRAM/designer/impl1/top.dtf
DualPortRAM/designer/impl1/top_fp
DualPortRAM/designer/impl1
DualPortRAM/smartgen/RAM2k8
DualPortRAM/synthesis/backup
DualPortRAM/synthesis/coreip
DualPortRAM/synthesis/syntmp
DualPortRAM/viewdraw/sch
DualPortRAM/viewdraw/sym
DualPortRAM/viewdraw/vf
DualPortRAM/viewdraw/wir
DualPortRAM/component
DualPortRAM/constraint
DualPortRAM/coreconsole
DualPortRAM/designer
DualPortRAM/hdl
DualPortRAM/phy_synthesis
DualPortRAM/simulation
DualPortRAM/smartgen
DualPortRAM/stimulus
DualPortRAM/synthesis
DualPortRAM/viewdraw
DualPortRAM

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