ddsVHDL/add_32.vhd
ddsVHDL/add_32.vhd.bak
ddsVHDL/db/altsyncram_h971.tdf
ddsVHDL/db/dds.(0).cnf.cdb
ddsVHDL/db/dds.(0).cnf.hdb
ddsVHDL/db/dds.(1).cnf.cdb
ddsVHDL/db/dds.(1).cnf.hdb
ddsVHDL/db/dds.(2).cnf.cdb
ddsVHDL/db/dds.(2).cnf.hdb
ddsVHDL/db/dds.(3).cnf.cdb
ddsVHDL/db/dds.(3).cnf.hdb
ddsVHDL/db/dds.(4).cnf.cdb
ddsVHDL/db/dds.(4).cnf.hdb
ddsVHDL/db/dds.asm.qmsg
ddsVHDL/db/dds.asm_labs.ddb
ddsVHDL/db/dds.cbx.xml
ddsVHDL/db/dds.cmp.bpm
ddsVHDL/db/dds.cmp.cdb
ddsVHDL/db/dds.cmp.ecobp
ddsVHDL/db/dds.cmp.hdb
ddsVHDL/db/dds.cmp.kpt
ddsVHDL/db/dds.cmp.logdb
ddsVHDL/db/dds.cmp.rdb
ddsVHDL/db/dds.cmp.tdb
ddsVHDL/db/dds.cmp0.ddb
ddsVHDL/db/dds.cmp2.ddb
ddsVHDL/db/dds.cmp_merge.kpt
ddsVHDL/db/dds.db_info
ddsVHDL/db/dds.eco.cdb
ddsVHDL/db/dds.eda.qmsg
ddsVHDL/db/dds.eds_overflow
ddsVHDL/db/dds.fit.qmsg
ddsVHDL/db/dds.hier_info
ddsVHDL/db/dds.hif
ddsVHDL/db/dds.lpc.html
ddsVHDL/db/dds.lpc.rdb
ddsVHDL/db/dds.lpc.txt
ddsVHDL/db/dds.map.bpm
ddsVHDL/db/dds.map.cdb
ddsVHDL/db/dds.map.ecobp
ddsVHDL/db/dds.map.hdb
ddsVHDL/db/dds.map.kpt
ddsVHDL/db/dds.map.logdb
ddsVHDL/db/dds.map.qmsg
ddsVHDL/db/dds.map_bb.cdb
ddsVHDL/db/dds.map_bb.hdb
ddsVHDL/db/dds.map_bb.logdb
ddsVHDL/db/dds.pre_map.cdb
ddsVHDL/db/dds.pre_map.hdb
ddsVHDL/db/dds.rpp.qmsg
ddsVHDL/db/dds.rtlv.hdb
ddsVHDL/db/dds.rtlv_sg.cdb
ddsVHDL/db/dds.rtlv_sg_swap.cdb
ddsVHDL/db/dds.sgate.rvd
ddsVHDL/db/dds.sgate_sm.rvd
ddsVHDL/db/dds.sgdiff.cdb
ddsVHDL/db/dds.sgdiff.hdb
ddsVHDL/db/dds.sim.cvwf
ddsVHDL/db/dds.sim.hdb
ddsVHDL/db/dds.sim.qmsg
ddsVHDL/db/dds.sim.rdb
ddsVHDL/db/dds.sld_design_entry.sci
ddsVHDL/db/dds.sld_design_entry_dsc.sci
ddsVHDL/db/dds.syn_hier_info
ddsVHDL/db/dds.tan.qmsg
ddsVHDL/db/dds.tis_db_list.ddb
ddsVHDL/db/dds.tmw_info
ddsVHDL/db/prev_cmp_dds.asm.qmsg
ddsVHDL/db/prev_cmp_dds.eda.qmsg
ddsVHDL/db/prev_cmp_dds.fit.qmsg
ddsVHDL/db/prev_cmp_dds.map.qmsg
ddsVHDL/db/prev_cmp_dds.qmsg
ddsVHDL/db/prev_cmp_dds.sim.qmsg
ddsVHDL/db/prev_cmp_dds.tan.qmsg
ddsVHDL/db/wed.wsf
ddsVHDL/dds.asm.rpt
ddsVHDL/dds.cdf
ddsVHDL/dds.done
ddsVHDL/dds.dpf
ddsVHDL/dds.eda.rpt
ddsVHDL/dds.fit.rpt
ddsVHDL/dds.fit.smsg
ddsVHDL/dds.fit.summary
ddsVHDL/dds.flow.rpt
ddsVHDL/dds.map.rpt
ddsVHDL/dds.map.summary
ddsVHDL/dds.pin
ddsVHDL/dds.pof
ddsVHDL/dds.qpf
ddsVHDL/dds.qsf
ddsVHDL/dds.qws
ddsVHDL/dds.sim.rpt
ddsVHDL/dds.sof
ddsVHDL/dds.tan.rpt
ddsVHDL/dds.tan.summary
ddsVHDL/dds.vhd
ddsVHDL/dds.vhd.bak
ddsVHDL/dds.vwf
ddsVHDL/dds_nativelink_simulation.rpt
ddsVHDL/incremental_db/compiled_partitions/dds.root_partition.cmp.atm
ddsVHDL/incremental_db/compiled_partitions/dds.root_partition.cmp.dfp
ddsVHDL/incremental_db/compiled_partitions/dds.root_partition.cmp.hdbx
ddsVHDL/incremental_db/compiled_partitions/dds.root_partition.cmp.kpt
ddsVHDL/incremental_db/compiled_partitions/dds.root_partition.cmp.logdb
ddsVHDL/incremental_db/compiled_partitions/dds.root_partition.cmp.rcf
ddsVHDL/incremental_db/compiled_partitions/dds.root_partition.map.atm
ddsVHDL/incremental_db/compiled_partitions/dds.root_partition.map.dpi
ddsVHDL/incremental_db/compiled_partitions/dds.root_partition.map.hdbx
ddsVHDL/incremental_db/compiled_partitions/dds.root_partition.map.kpt
ddsVHDL/incremental_db/README
ddsVHDL/romdata.mif
ddsVHDL/rom_10.bsf
ddsVHDL/rom_10.cmp
ddsVHDL/rom_10.qip
ddsVHDL/rom_10.vhd
ddsVHDL/rom_10_wave0.jpg
ddsVHDL/rom_10_waveforms.html
ddsVHDL/simulation/dds.cr.mti
ddsVHDL/simulation/dds.mpf
ddsVHDL/simulation/modelsim/altera_mf/alt3pram/behavior.asm
ddsVHDL/simulation/modelsim/altera_mf/alt3pram/behavior.dat
ddsVHDL/simulation/modelsim/altera_mf/alt3pram/_primary.dat
ddsVHDL/simulation/modelsim/altera_mf/altaccumulate/behaviour.asm
ddsVHDL/simulation/modelsim/altera_mf/altaccumulate/behaviour.dat
ddsVHDL/simulation/modelsim/altera_mf/altaccumulate/_primary.dat
ddsVHDL/simulation/modelsim/altera_mf/altcam/behave.asm
ddsVHDL/simulation/modelsim/altera_mf/altcam/behave.dat
ddsVHDL/simulation/modelsim/altera_mf/altcam/_primary.dat
ddsVHDL/simulation/modelsim/altera_mf/altclklock/behavior.asm
ddsVHDL/simulation/modelsim/altera_mf/altclklock/behavior.dat
ddsVHDL/simulation/modelsim/altera_mf/altclklock/_primary.dat
ddsVHDL/simulation/modelsim/altera_mf/altddio_bidir/struct.asm
ddsVHDL/simulation/modelsim/altera_mf/altddio_bidir/struct.dat
ddsVHDL/simulation/modelsim/altera_mf/altddio_bidir/_primary.dat
ddsVHDL/simulation/modelsim/altera_mf/altddio_in/behave.asm
ddsVHDL/simulation/modelsim/altera_mf/altddio_in/behave.dat
ddsVHDL/simulation/modelsim/altera_mf/altddio_in/_primary.dat
ddsVHDL/simulation/modelsim/altera_mf/altddio_out/behave.asm
ddsVHDL/simulation/modelsim/altera_mf/altddio_out/behave.dat
ddsVHDL/simulation/modelsim/altera_mf/altddio_out/_primary.dat
ddsVHDL/simulation/modelsim/altera_mf/altdpram/behavior.asm
ddsVHDL/simulation/modelsim/altera_mf/altdpram/behavior.dat
ddsVHDL/simulation/modelsim/altera_mf/altdpram/_primary.dat
ddsVHDL/simulation/modelsim/altera_mf/altdq_dqs/translated.asm
ddsVHDL/simulation/modelsim/altera_mf/altdq_dqs/translated.dat
ddsVHDL/simulation/modelsim/altera_mf/altdq_dqs/_primary.dat
ddsVHDL/simulation/modelsim/altera_mf/altera_common_conversion/body.asm
ddsVHDL/simulation/model