CDN加速镜像 | 设为首页 | 加入收藏夹
当前位置: 首页 资源下载 源码下载 嵌入式/单片机编程 VHDL编程

文件名称:I2C

  • 所属分类:
  • 标签属性:
  • 上传时间:
    2012-11-16
  • 文件大小:
    201.09kb
  • 已下载:
    0次
  • 提 供 者:
  • 相关连接:
  • 下载说明:
    别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容来自于网络,使用问题请自行百度

I2C 接口 用VERILOG 实现的基于FPGA的I2C slave -FPGA I2C SLAVE
(系统自动生成,下载前可以参看下载内容)

下载文件列表

I2C/design/I2CSlave.prd
I2C/design/I2CSlave.prj
I2C/design/I2Cslave.v
I2C/design/myram.v
I2C/design/rev_1/.recordref
I2C/design/rev_1/AutoConstraint_I2Cslave.sdc
I2C/design/rev_1/AutoConstraint_myRAM.sdc
I2C/design/rev_1/I2Cslave.edf
I2C/design/rev_1/I2Cslave.fse
I2C/design/rev_1/I2Cslave.htm
I2C/design/rev_1/I2Cslave.ncf
I2C/design/rev_1/I2Cslave.srd
I2C/design/rev_1/I2Cslave.srm
I2C/design/rev_1/I2Cslave.srr
I2C/design/rev_1/I2Cslave.srs
I2C/design/rev_1/I2Cslave.tlg
I2C/design/rev_1/myram.edf
I2C/design/rev_1/myram.fse
I2C/design/rev_1/myram.htm
I2C/design/rev_1/myram.ncf
I2C/design/rev_1/myram.srd
I2C/design/rev_1/myram.srm
I2C/design/rev_1/myram.srr
I2C/design/rev_1/myram.srs
I2C/design/rev_1/myram.tlg
I2C/design/rev_1/rpt_I2Cslave.areasrr
I2C/design/rev_1/rpt_I2Cslave_areasrr.htm
I2C/design/rev_1/rpt_myRAM.areasrr
I2C/design/rev_1/rpt_myRAM_areasrr.htm
I2C/design/rev_1/rpt_slave_top.areasrr
I2C/design/rev_1/rpt_slave_top_areasrr.htm
I2C/design/rev_1/slave_top.edf
I2C/design/rev_1/slave_top.fse
I2C/design/rev_1/slave_top.htm
I2C/design/rev_1/slave_top.ncf
I2C/design/rev_1/slave_top.srd
I2C/design/rev_1/slave_top.srm
I2C/design/rev_1/slave_top.srr
I2C/design/rev_1/slave_top.srs
I2C/design/rev_1/slave_top.tlg
I2C/design/rev_1/syntmp/I2Cslave.msg
I2C/design/rev_1/syntmp/I2Cslave.plg
I2C/design/rev_1/syntmp/I2Cslave_flink.htm
I2C/design/rev_1/syntmp/I2Cslave_srr.htm
I2C/design/rev_1/syntmp/I2Cslave_toc.htm
I2C/design/rev_1/syntmp/myram.msg
I2C/design/rev_1/syntmp/myram.plg
I2C/design/rev_1/syntmp/myram_flink.htm
I2C/design/rev_1/syntmp/myram_srr.htm
I2C/design/rev_1/syntmp/myram_toc.htm
I2C/design/rev_1/syntmp/slave_top.msg
I2C/design/rev_1/syntmp/slave_top.plg
I2C/design/rev_1/syntmp/slave_top_flink.htm
I2C/design/rev_1/syntmp/slave_top_srr.htm
I2C/design/rev_1/syntmp/slave_top_toc.htm
I2C/design/rev_1/syntmp/timescale_flink.htm
I2C/design/rev_1/syntmp/timescale_srr.htm
I2C/design/rev_1/syntmp/timescale_toc.htm
I2C/design/rev_1/syntmp
I2C/design/rev_1/timescale.htm
I2C/design/rev_1/timescale.srr
I2C/design/rev_1/traplog.tlg
I2C/design/rev_1/verif/I2Cslave.vif
I2C/design/rev_1/verif/myram.vif
I2C/design/rev_1/verif/slave_top.vif
I2C/design/rev_1/verif
I2C/design/rev_1
I2C/design/sim/all.do
I2C/design/sim/i2c_master_bit_ctrl.v
I2C/design/sim/i2c_master_byte_ctrl.v
I2C/design/sim/i2c_master_defines.v
I2C/design/sim/i2c_master_top.v
I2C/design/sim/Sim_Behav.bat
I2C/design/sim/timescale.v
I2C/design/sim/transcript
I2C/design/sim/tst_bench_top.v
I2C/design/sim/vish_stacktrace.vstf
I2C/design/sim/vsim.wlf
I2C/design/sim/wb_master_model.v
I2C/design/sim/work/@i2@cslave/verilog.asm
I2C/design/sim/work/@i2@cslave/_primary.dat
I2C/design/sim/work/@i2@cslave/_primary.vhd
I2C/design/sim/work/@i2@cslave
I2C/design/sim/work/i2c_master_bit_ctrl/verilog.asm
I2C/design/sim/work/i2c_master_bit_ctrl/_primary.dat
I2C/design/sim/work/i2c_master_bit_ctrl/_primary.vhd
I2C/design/sim/work/i2c_master_bit_ctrl
I2C/design/sim/work/i2c_master_byte_ctrl/verilog.asm
I2C/design/sim/work/i2c_master_byte_ctrl/_primary.dat
I2C/design/sim/work/i2c_master_byte_ctrl/_primary.vhd
I2C/design/sim/work/i2c_master_byte_ctrl
I2C/design/sim/work/i2c_master_top/verilog.asm
I2C/design/sim/work/i2c_master_top/_primary.dat
I2C/design/sim/work/i2c_master_top/_primary.vhd
I2C/design/sim/work/i2c_master_top
I2C/design/sim/work/my@r@a@m/verilog.asm
I2C/design/sim/work/my@r@a@m/_primary.dat
I2C/design/sim/work/my@r@a@m/_primary.vhd
I2C/design/sim/work/my@r@a@m
I2C/design/sim/work/tst_bench_top/verilog.asm
I2C/design/sim/work/tst_bench_top/_primary.dat
I2C/design/sim/work/tst_bench_top/_primary.vhd
I2C/design/sim/work/tst_bench_top
I2C/design/sim/work/wb_master_model/verilog.asm
I2C/design/sim/work/wb_master_model/_primary.dat
I2C/design/sim/work/wb_master_model/_primary.vhd
I2C/design/sim/work/wb_master_model
I2C/design/sim/work/_info
I2C/design/sim/work
I2C/design/sim
I2C/design/syntmp.msg
I2C/design/test.prd
I2C/design/test.prj
I2C/design
I2C/I2C Slave设计笔记.doc
I2C

相关说明

  • 本站资源为会员上传分享交流与学习,如有侵犯您的权益,请联系我们删除.
  • 搜珍网是交换下载平台,只提供交流渠道,下载内容来自于网络,除下载问题外,其它问题请自行百度。更多...
  • 本站已设置防盗链,请勿用迅雷、QQ旋风等下载软件下载资源,下载后用WinRAR最新版进行解压.
  • 如果您发现内容无法下载,请稍后再次尝试;或换浏览器;或者到消费记录里找到下载记录反馈给我们.
  • 下载后发现下载的内容跟说明不相乎,请到消费记录里找到下载记录反馈给我们,经确认后退回积分.
  • 如下载前有疑问,可以通过点击"提供者"的名字,查看对方的联系方式,联系对方咨询.

相关评论

暂无评论内容.

发表评论

*快速评论: 推荐 一般 有密码 和说明不符 不是源码或资料 文件不全 不能解压 纯粹是垃圾
*内  容:
*验 证 码:
搜珍网 www.dssz.com