文件名称:spi_latest.tar
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- 上传时间:2012-11-16
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文件大小:2.5mb
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spi接口 verilog版本, Synchronous serial interfaces are widely used to provide economical board-level interfaces between different devices such as microcontrollers, DACs, ADCs and other. Although there is no single standard for a synchronous serial bus, there are industry-wide accepted guidelines based on two most popular implementations:-spi interface, verilog version, Synchronous serial interfaces are widely used to provide economical board-level interfaces between different devices such as microcontrollers, DACs, ADCs and other. Although there is no single standard for a synchronous serial bus, there are industry-wide accepted guidelines based on two most popular implementations:
相关搜索: SPI Verilog
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下载文件列表
spi/
spi/branches/
spi/tags/
spi/tags/rel_2/
spi/tags/rel_2/bench/
spi/tags/rel_2/bench/verilog/
spi/tags/rel_2/bench/verilog/wb_master_model.v
spi/tags/rel_2/bench/verilog/tb_spi_top.v
spi/tags/rel_2/bench/verilog/spi_slave_model.v
spi/tags/rel_2/sim/
spi/tags/rel_2/sim/run/
spi/tags/rel_2/sim/run/tcl.scr
spi/tags/rel_2/sim/run/sim
spi/tags/rel_2/rtl/
spi/tags/rel_2/rtl/verilog/
spi/tags/rel_2/rtl/verilog/timescale.v
spi/tags/rel_2/rtl/verilog/spi_top.v
spi/tags/rel_2/rtl/verilog/spi_clgen.v
spi/tags/rel_2/rtl/verilog/spi_defines.v
spi/tags/rel_2/rtl/verilog/spi_shift.v
spi/tags/rel_2/doc/
spi/tags/rel_2/doc/spi.pdf
spi/tags/rel_2/doc/src/
spi/tags/rel_2/doc/src/spi.doc
spi/tags/rel_8/
spi/tags/rel_8/bench/
spi/tags/rel_8/bench/verilog/
spi/tags/rel_8/bench/verilog/wb_master_model.v
spi/tags/rel_8/bench/verilog/tb_spi_top.v
spi/tags/rel_8/bench/verilog/spi_slave_model.v
spi/tags/rel_8/sim/
spi/tags/rel_8/sim/rtl_sim/
spi/tags/rel_8/sim/rtl_sim/run/
spi/tags/rel_8/sim/rtl_sim/run/sim.fl
spi/tags/rel_8/sim/rtl_sim/run/rtl.fl
spi/tags/rel_8/sim/rtl_sim/run/run_sim
spi/tags/rel_8/rtl/
spi/tags/rel_8/rtl/verilog/
spi/tags/rel_8/rtl/verilog/timescale.v
spi/tags/rel_8/rtl/verilog/spi_top.v
spi/tags/rel_8/rtl/verilog/spi_clgen.v
spi/tags/rel_8/rtl/verilog/spi_defines.v
spi/tags/rel_8/rtl/verilog/spi_shift.v
spi/tags/rel_8/doc/
spi/tags/rel_8/doc/spi.pdf
spi/tags/rel_8/doc/src/
spi/tags/rel_8/doc/src/spi.doc
spi/tags/asyst_2/
spi/tags/asyst_2/rtl/
spi/tags/asyst_2/rtl/verilog/
spi/tags/asyst_2/rtl/verilog/timescale.v
spi/tags/asyst_2/rtl/verilog/spi_top.v
spi/tags/asyst_2/rtl/verilog/spi_clgen.v
spi/tags/asyst_2/rtl/verilog/spi_defines.v
spi/tags/asyst_2/rtl/verilog/spi_shift.v
spi/tags/rel_4/
spi/tags/rel_4/bench/
spi/tags/rel_4/bench/verilog/
spi/tags/rel_4/bench/verilog/wb_master_model.v
spi/tags/rel_4/bench/verilog/tb_spi_top.v
spi/tags/rel_4/bench/verilog/spi_slave_model.v
spi/tags/rel_4/sim/
spi/tags/rel_4/sim/run/
spi/tags/rel_4/sim/run/tcl.scr
spi/tags/rel_4/sim/run/sim
spi/tags/rel_4/rtl/
spi/tags/rel_4/rtl/verilog/
spi/tags/rel_4/rtl/verilog/timescale.v
spi/tags/rel_4/rtl/verilog/spi_top.v
spi/tags/rel_4/rtl/verilog/spi_clgen.v
spi/tags/rel_4/rtl/verilog/spi_defines.v
spi/tags/rel_4/rtl/verilog/spi_shift.v
spi/tags/rel_4/doc/
spi/tags/rel_4/doc/spi.pdf
spi/tags/rel_4/doc/src/
spi/tags/rel_4/doc/src/spi.doc
spi/tags/rel_6/
spi/tags/rel_6/bench/
spi/tags/rel_6/bench/verilog/
spi/tags/rel_6/bench/verilog/wb_master_model.v
spi/tags/rel_6/bench/verilog/tb_spi_top.v
spi/tags/rel_6/bench/verilog/spi_slave_model.v
spi/tags/rel_6/sim/
spi/tags/rel_6/sim/run/
spi/tags/rel_6/sim/run/tcl.scr
spi/tags/rel_6/sim/run/sim
spi/tags/rel_6/rtl/
spi/tags/rel_6/rtl/verilog/
spi/tags/rel_6/rtl/verilog/timescale.v
spi/tags/rel_6/rtl/verilog/spi_top.v
spi/tags/rel_6/rtl/verilog/spi_clgen.v
spi/tags/rel_6/rtl/verilog/spi_defines.v
spi/tags/rel_6/rtl/verilog/spi_shift.v
spi/tags/rel_6/doc/
spi/tags/rel_6/doc/spi.pdf
spi/tags/rel_6/doc/src/
spi/tags/rel_6/doc/src/spi.doc
spi/tags/rel_5/
spi/tags/rel_5/bench/
spi/tags/rel_5/bench/verilog/
spi/tags/rel_5/bench/verilog/wb_master_model.v
spi/tags/rel_5/bench/verilog/tb_spi_top.v
spi/tags/rel_5/bench/verilog/spi_slave_model.v
spi/tags/rel_5/sim/
spi/tags/rel_5/sim/run/
spi/tags/rel_5/sim/run/tcl.scr
spi/tags/rel_5/sim/run/sim
spi/tags/rel_5/rtl/
spi/tags/rel_5/rtl/verilog/
spi/tags/rel_5/rtl/verilog/timescale.v
spi/tags/rel_5/rtl/verilog/spi_top.v
spi/tags/rel_5/rtl/verilog/spi_clgen.v
spi/tags/rel_5/rtl/verilog/spi_defines.v
spi/tags/rel_5/rtl/verilog/spi_shift.v
spi/tags/rel_5/doc/
spi/tags/rel_5/doc/spi.pdf
spi/tags/rel_5/doc/src/
spi/tags/rel_5/doc/src/spi.doc
spi/tags/asyst_3/
spi/tags/asyst_3/rtl/
spi/tags/asyst_3/rtl/verilog/
spi/tags/asyst_3/rtl/verilog/timescale.v
spi/tags/asyst_3/rtl/verilog/spi_top.v
spi/tags/asyst_3/rtl/verilog/spi_clgen.v
spi/tags/asyst_3/rtl/verilog/spi_defines.v
spi/tags/asyst_3/rtl/verilog/spi_shift.v
spi/tags/rel_1/
spi/tags/rel_1/bench/
spi/tags/rel_1/bench/verilog/
spi/tags/rel_1/bench/verilog/wb_master_model.v
spi/tags/rel_1/bench/verilog/tb_spi_top.v
spi/tags/rel_1/bench/verilog/spi_slave_model.v
spi/tags/rel_1/sim/
spi/tags/rel_1/sim/run/
spi/tags/rel_1/sim/run/tcl.scr
spi/tags/rel_1/sim/run/sim
spi/tags/rel_1/rtl/
spi/tags/rel_1/rtl/verilog/
spi/tags/rel_1/rtl/verilog/timescale.v
spi/tags/rel_1/rtl/verilog/spi_top.v
spi/tags/rel_1/rtl/verilog/spi_clgen.v
spi/tags/rel_1/rtl/verilog/spi_defines.v
spi/tags/rel_1/rtl/verilog/spi_shift.v
spi/tags/rel_1/doc/
spi/tags/rel_1/doc/spi.pdf
spi/tags/rel_1/doc/src/
spi/tags/rel_1/doc/src/spi.doc
spi/tags/rel_3/
spi/tags/rel_3/bench/
spi/tags/rel_3/bench/verilog/
spi/tags/rel_3/bench/verilog/wb_master_model.v
spi/tags/rel_3/bench/verilog/tb_spi_top.v
spi/tags/rel_3/bench/verilog/spi_slave_model.v
spi/tags/rel_3/sim/
spi/tags/rel_3/sim/run/
spi/tags/rel_3/sim/run/tcl.scr
spi/tags/rel_3/sim/run/sim
spi/tags/rel_3/rtl/
spi/tags/rel_3/rtl/verilog/
spi/tags/rel_3/rtl/verilog/timescale.v
spi/tags/rel_3/rtl/verilog/spi_top.v
spi/tags/rel_3/rtl/verilog/spi_clgen.v
spi/tags/rel_3/rtl/verilog/spi_defines.v
spi/tags/rel_3/rtl/verilog/spi_s
spi/branches/
spi/tags/
spi/tags/rel_2/
spi/tags/rel_2/bench/
spi/tags/rel_2/bench/verilog/
spi/tags/rel_2/bench/verilog/wb_master_model.v
spi/tags/rel_2/bench/verilog/tb_spi_top.v
spi/tags/rel_2/bench/verilog/spi_slave_model.v
spi/tags/rel_2/sim/
spi/tags/rel_2/sim/run/
spi/tags/rel_2/sim/run/tcl.scr
spi/tags/rel_2/sim/run/sim
spi/tags/rel_2/rtl/
spi/tags/rel_2/rtl/verilog/
spi/tags/rel_2/rtl/verilog/timescale.v
spi/tags/rel_2/rtl/verilog/spi_top.v
spi/tags/rel_2/rtl/verilog/spi_clgen.v
spi/tags/rel_2/rtl/verilog/spi_defines.v
spi/tags/rel_2/rtl/verilog/spi_shift.v
spi/tags/rel_2/doc/
spi/tags/rel_2/doc/spi.pdf
spi/tags/rel_2/doc/src/
spi/tags/rel_2/doc/src/spi.doc
spi/tags/rel_8/
spi/tags/rel_8/bench/
spi/tags/rel_8/bench/verilog/
spi/tags/rel_8/bench/verilog/wb_master_model.v
spi/tags/rel_8/bench/verilog/tb_spi_top.v
spi/tags/rel_8/bench/verilog/spi_slave_model.v
spi/tags/rel_8/sim/
spi/tags/rel_8/sim/rtl_sim/
spi/tags/rel_8/sim/rtl_sim/run/
spi/tags/rel_8/sim/rtl_sim/run/sim.fl
spi/tags/rel_8/sim/rtl_sim/run/rtl.fl
spi/tags/rel_8/sim/rtl_sim/run/run_sim
spi/tags/rel_8/rtl/
spi/tags/rel_8/rtl/verilog/
spi/tags/rel_8/rtl/verilog/timescale.v
spi/tags/rel_8/rtl/verilog/spi_top.v
spi/tags/rel_8/rtl/verilog/spi_clgen.v
spi/tags/rel_8/rtl/verilog/spi_defines.v
spi/tags/rel_8/rtl/verilog/spi_shift.v
spi/tags/rel_8/doc/
spi/tags/rel_8/doc/spi.pdf
spi/tags/rel_8/doc/src/
spi/tags/rel_8/doc/src/spi.doc
spi/tags/asyst_2/
spi/tags/asyst_2/rtl/
spi/tags/asyst_2/rtl/verilog/
spi/tags/asyst_2/rtl/verilog/timescale.v
spi/tags/asyst_2/rtl/verilog/spi_top.v
spi/tags/asyst_2/rtl/verilog/spi_clgen.v
spi/tags/asyst_2/rtl/verilog/spi_defines.v
spi/tags/asyst_2/rtl/verilog/spi_shift.v
spi/tags/rel_4/
spi/tags/rel_4/bench/
spi/tags/rel_4/bench/verilog/
spi/tags/rel_4/bench/verilog/wb_master_model.v
spi/tags/rel_4/bench/verilog/tb_spi_top.v
spi/tags/rel_4/bench/verilog/spi_slave_model.v
spi/tags/rel_4/sim/
spi/tags/rel_4/sim/run/
spi/tags/rel_4/sim/run/tcl.scr
spi/tags/rel_4/sim/run/sim
spi/tags/rel_4/rtl/
spi/tags/rel_4/rtl/verilog/
spi/tags/rel_4/rtl/verilog/timescale.v
spi/tags/rel_4/rtl/verilog/spi_top.v
spi/tags/rel_4/rtl/verilog/spi_clgen.v
spi/tags/rel_4/rtl/verilog/spi_defines.v
spi/tags/rel_4/rtl/verilog/spi_shift.v
spi/tags/rel_4/doc/
spi/tags/rel_4/doc/spi.pdf
spi/tags/rel_4/doc/src/
spi/tags/rel_4/doc/src/spi.doc
spi/tags/rel_6/
spi/tags/rel_6/bench/
spi/tags/rel_6/bench/verilog/
spi/tags/rel_6/bench/verilog/wb_master_model.v
spi/tags/rel_6/bench/verilog/tb_spi_top.v
spi/tags/rel_6/bench/verilog/spi_slave_model.v
spi/tags/rel_6/sim/
spi/tags/rel_6/sim/run/
spi/tags/rel_6/sim/run/tcl.scr
spi/tags/rel_6/sim/run/sim
spi/tags/rel_6/rtl/
spi/tags/rel_6/rtl/verilog/
spi/tags/rel_6/rtl/verilog/timescale.v
spi/tags/rel_6/rtl/verilog/spi_top.v
spi/tags/rel_6/rtl/verilog/spi_clgen.v
spi/tags/rel_6/rtl/verilog/spi_defines.v
spi/tags/rel_6/rtl/verilog/spi_shift.v
spi/tags/rel_6/doc/
spi/tags/rel_6/doc/spi.pdf
spi/tags/rel_6/doc/src/
spi/tags/rel_6/doc/src/spi.doc
spi/tags/rel_5/
spi/tags/rel_5/bench/
spi/tags/rel_5/bench/verilog/
spi/tags/rel_5/bench/verilog/wb_master_model.v
spi/tags/rel_5/bench/verilog/tb_spi_top.v
spi/tags/rel_5/bench/verilog/spi_slave_model.v
spi/tags/rel_5/sim/
spi/tags/rel_5/sim/run/
spi/tags/rel_5/sim/run/tcl.scr
spi/tags/rel_5/sim/run/sim
spi/tags/rel_5/rtl/
spi/tags/rel_5/rtl/verilog/
spi/tags/rel_5/rtl/verilog/timescale.v
spi/tags/rel_5/rtl/verilog/spi_top.v
spi/tags/rel_5/rtl/verilog/spi_clgen.v
spi/tags/rel_5/rtl/verilog/spi_defines.v
spi/tags/rel_5/rtl/verilog/spi_shift.v
spi/tags/rel_5/doc/
spi/tags/rel_5/doc/spi.pdf
spi/tags/rel_5/doc/src/
spi/tags/rel_5/doc/src/spi.doc
spi/tags/asyst_3/
spi/tags/asyst_3/rtl/
spi/tags/asyst_3/rtl/verilog/
spi/tags/asyst_3/rtl/verilog/timescale.v
spi/tags/asyst_3/rtl/verilog/spi_top.v
spi/tags/asyst_3/rtl/verilog/spi_clgen.v
spi/tags/asyst_3/rtl/verilog/spi_defines.v
spi/tags/asyst_3/rtl/verilog/spi_shift.v
spi/tags/rel_1/
spi/tags/rel_1/bench/
spi/tags/rel_1/bench/verilog/
spi/tags/rel_1/bench/verilog/wb_master_model.v
spi/tags/rel_1/bench/verilog/tb_spi_top.v
spi/tags/rel_1/bench/verilog/spi_slave_model.v
spi/tags/rel_1/sim/
spi/tags/rel_1/sim/run/
spi/tags/rel_1/sim/run/tcl.scr
spi/tags/rel_1/sim/run/sim
spi/tags/rel_1/rtl/
spi/tags/rel_1/rtl/verilog/
spi/tags/rel_1/rtl/verilog/timescale.v
spi/tags/rel_1/rtl/verilog/spi_top.v
spi/tags/rel_1/rtl/verilog/spi_clgen.v
spi/tags/rel_1/rtl/verilog/spi_defines.v
spi/tags/rel_1/rtl/verilog/spi_shift.v
spi/tags/rel_1/doc/
spi/tags/rel_1/doc/spi.pdf
spi/tags/rel_1/doc/src/
spi/tags/rel_1/doc/src/spi.doc
spi/tags/rel_3/
spi/tags/rel_3/bench/
spi/tags/rel_3/bench/verilog/
spi/tags/rel_3/bench/verilog/wb_master_model.v
spi/tags/rel_3/bench/verilog/tb_spi_top.v
spi/tags/rel_3/bench/verilog/spi_slave_model.v
spi/tags/rel_3/sim/
spi/tags/rel_3/sim/run/
spi/tags/rel_3/sim/run/tcl.scr
spi/tags/rel_3/sim/run/sim
spi/tags/rel_3/rtl/
spi/tags/rel_3/rtl/verilog/
spi/tags/rel_3/rtl/verilog/timescale.v
spi/tags/rel_3/rtl/verilog/spi_top.v
spi/tags/rel_3/rtl/verilog/spi_clgen.v
spi/tags/rel_3/rtl/verilog/spi_defines.v
spi/tags/rel_3/rtl/verilog/spi_s
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