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文件名称:ssss

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    317.15kb
  • 已下载：
    0次
  • 提 供 者：
    刘****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

spartan—3a对ddr2读写控制源程序，有verilog和vhdl版本-spartan-3a ddr2 read and write control of the source, there are versions of verilog and vhdl
相关搜索： ddr2 verilog

(系统自动生成,下载前可以参看下载内容)

下载文件列表

ssss/ddr2_sdram/folder_details.txt
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/datasheet.txt
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/design_testing.txt
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/par/create_ise.bat
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/par/icon_coregen.xco
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/par/ila_coregen.xco
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/par/ise_flow.bat
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/par/ise_run.txt
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/par/makeproj.bat
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/par/mem_interface_top.ut
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/par/readme.txt
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/par/set_ise_prop.tcl
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/par/vio_coregen.xco
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/par/vlog_bl8.bit
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/par/vlog_bl8.cdc
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/par/vlog_bl8.ucf
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_addr_gen_0.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_cal_ctl.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_cal_top.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_clk_dcm.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_cmd_fsm_0.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_cmp_data_0.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_controller_0.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_controller_iobs_0.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_data_gen_0.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_data_path_0.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_data_path_iobs_0.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_data_read_0.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_data_read_controller_0.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_data_write_0.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_dqs_delay.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_fifo_0_wr_en_0.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_fifo_1_wr_en_0.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_infrastructure.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_infrastructure_iobs_0.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_infrastructure_top.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_iobs_0.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_main_0.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_parameters_0.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_ram8d_0.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_ram8d_1.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_rd_gray_cntr.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_s3_dm_iob.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_s3_dqs_iob.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_s3_dq_iob.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_tap_dly.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_test_bench_0.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_top_0.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/rtl/vlog_bl8_wr_gray_cntr.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/sim/ddr2_model.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/sim/ddr2_model_parameters.vh
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/sim/glbl.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/sim/sim.do
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/sim/sim_tb_top.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/sim/wiredly.v
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/synth/mem_interface_top_synp.sdc
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/synth/script_synp.tcl
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/synth/vlog_bl8.lso
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/synth/vlog_bl8.prj
ssss/ddr2_sdram/verilog/vlog_bl8/example_design/vlog_bl8.cpj
ssss/ddr2_sdram/vhdl/vhdl_bl4/example_design/datasheet.txt
ssss/ddr2_sdram/vhdl/vhdl_bl4/example_design/design_testing.txt
ssss/ddr2_sdram/vhdl/vhdl_bl4/example_design/par/create_ise.bat
ssss/ddr2_sdram/vhdl/vhdl_bl4/example_design/par/icon_coregen.xco
ssss/ddr2_sdram/vhdl/vhdl_bl4/example_design/par/ila_coregen.xco
ssss/ddr2_sdram/vhdl/vhdl_bl4/example_design/par/ise_flow.bat
ssss/ddr2_sdram/vhdl/vhdl_bl4/example_design/par/ise_run.txt
ssss/ddr2_sdram/vhdl/vhdl_bl4/example_design/par/makeproj.bat
ssss/ddr2_sdram/vhdl/vhdl_bl4/example_design/par/mem_interface_top.ut
ssss/ddr2_sdram/vhdl/vhdl_bl4/example_design/par/readme.txt
ssss/ddr2_sdram/vhdl/vhdl_bl4/example_design/par/set_ise_prop.tcl
ssss/ddr2_sdram/vhdl/vhdl_bl4/example_design/par/vhdl_bl4.bit
ssss/ddr2_sdram/vhdl/vhdl_bl4/example_design/par/vhdl_bl

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