文件名称:RISC_SPM
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- 上传时间:2012-11-16
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文件大小:120.79kb
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简单risc cpu设计,本人通过书中的代码,又加了一些,已通过仿真。-Risc cpu simple design, I code by the book, but also added some, has been through simulation.
相关搜索: cpu设计
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下载文件列表
RISC_SPM/work/_info
RISC_SPM/work/_vmake
RISC_SPM/work/@r@i@s@c_@s@p@m/_primary.vhd
RISC_SPM/work/@r@i@s@c_@s@p@m/_primary.dbs
RISC_SPM/work/@r@i@s@c_@s@p@m/_primary.dat
RISC_SPM/work/@r@i@s@c_@s@p@m/verilog.asm
RISC_SPM/work/@r@i@s@c_@s@p@m/verilog.rw
RISC_SPM/work/@processing_@unit/_primary.vhd
RISC_SPM/work/@processing_@unit/_primary.dbs
RISC_SPM/work/@processing_@unit/_primary.dat
RISC_SPM/work/@processing_@unit/verilog.asm
RISC_SPM/work/@processing_@unit/verilog.rw
RISC_SPM/work/@register_@unit/_primary.vhd
RISC_SPM/work/@register_@unit/_primary.dbs
RISC_SPM/work/@register_@unit/_primary.dat
RISC_SPM/work/@register_@unit/verilog.asm
RISC_SPM/work/@register_@unit/verilog.rw
RISC_SPM/work/@d_flop/_primary.vhd
RISC_SPM/work/@d_flop/_primary.dbs
RISC_SPM/work/@d_flop/_primary.dat
RISC_SPM/work/@d_flop/verilog.asm
RISC_SPM/work/@d_flop/verilog.rw
RISC_SPM/work/@address_@register/_primary.vhd
RISC_SPM/work/@address_@register/_primary.dbs
RISC_SPM/work/@address_@register/_primary.dat
RISC_SPM/work/@address_@register/verilog.asm
RISC_SPM/work/@address_@register/verilog.rw
RISC_SPM/work/@instruction_@register/_primary.vhd
RISC_SPM/work/@instruction_@register/_primary.dbs
RISC_SPM/work/@instruction_@register/_primary.dat
RISC_SPM/work/@instruction_@register/verilog.asm
RISC_SPM/work/@instruction_@register/verilog.rw
RISC_SPM/work/@program_@counter/_primary.vhd
RISC_SPM/work/@program_@counter/_primary.dbs
RISC_SPM/work/@program_@counter/_primary.dat
RISC_SPM/work/@program_@counter/verilog.asm
RISC_SPM/work/@program_@counter/verilog.rw
RISC_SPM/work/@multiplexer_5ch/_primary.vhd
RISC_SPM/work/@multiplexer_5ch/_primary.dbs
RISC_SPM/work/@multiplexer_5ch/_primary.dat
RISC_SPM/work/@multiplexer_5ch/verilog.asm
RISC_SPM/work/@multiplexer_5ch/verilog.rw
RISC_SPM/work/@multiplexer_3ch/_primary.vhd
RISC_SPM/work/@multiplexer_3ch/_primary.dbs
RISC_SPM/work/@multiplexer_3ch/_primary.dat
RISC_SPM/work/@multiplexer_3ch/verilog.asm
RISC_SPM/work/@multiplexer_3ch/verilog.rw
RISC_SPM/work/@alu_@r@i@s@c/_primary.vhd
RISC_SPM/work/@alu_@r@i@s@c/_primary.dbs
RISC_SPM/work/@alu_@r@i@s@c/_primary.dat
RISC_SPM/work/@alu_@r@i@s@c/verilog.asm
RISC_SPM/work/@alu_@r@i@s@c/verilog.rw
RISC_SPM/work/@control_@unit/_primary.vhd
RISC_SPM/work/@control_@unit/_primary.dbs
RISC_SPM/work/@control_@unit/_primary.dat
RISC_SPM/work/@control_@unit/verilog.asm
RISC_SPM/work/@control_@unit/verilog.rw
RISC_SPM/work/@memory_@unit/_primary.vhd
RISC_SPM/work/@memory_@unit/_primary.dbs
RISC_SPM/work/@memory_@unit/_primary.dat
RISC_SPM/work/@memory_@unit/verilog.asm
RISC_SPM/work/@memory_@unit/verilog.rw
RISC_SPM/work/test_@r@i@s@c_@s@p@m/_primary.vhd
RISC_SPM/work/test_@r@i@s@c_@s@p@m/_primary.dbs
RISC_SPM/work/test_@r@i@s@c_@s@p@m/_primary.dat
RISC_SPM/work/test_@r@i@s@c_@s@p@m/verilog.asm
RISC_SPM/work/test_@r@i@s@c_@s@p@m/verilog.rw
RISC_SPM/work/@clock_@unit/_primary.vhd
RISC_SPM/work/@clock_@unit/_primary.dbs
RISC_SPM/work/@clock_@unit/_primary.dat
RISC_SPM/work/@clock_@unit/verilog.asm
RISC_SPM/work/@clock_@unit/verilog.rw
RISC_SPM/RISC_SPM.v
RISC_SPM/test_RISC_SPM.v
RISC_SPM/RISC_SPM.v.bak
RISC_SPM/Clock_Unit.v
RISC_SPM/vsim.wlf
RISC_SPM/test_RISC_SPM.v.bak
RISC_SPM/RISC_SPM.mpf
RISC_SPM/RISC_SPM.cr.mti
RISC_SPM/work/_temp
RISC_SPM/work/@r@i@s@c_@s@p@m
RISC_SPM/work/@processing_@unit
RISC_SPM/work/@register_@unit
RISC_SPM/work/@d_flop
RISC_SPM/work/@address_@register
RISC_SPM/work/@instruction_@register
RISC_SPM/work/@program_@counter
RISC_SPM/work/@multiplexer_5ch
RISC_SPM/work/@multiplexer_3ch
RISC_SPM/work/@alu_@r@i@s@c
RISC_SPM/work/@control_@unit
RISC_SPM/work/@memory_@unit
RISC_SPM/work/test_@r@i@s@c_@s@p@m
RISC_SPM/work/@clock_@unit
RISC_SPM/work
RISC_SPM
RISC_SPM/work/_vmake
RISC_SPM/work/@r@i@s@c_@s@p@m/_primary.vhd
RISC_SPM/work/@r@i@s@c_@s@p@m/_primary.dbs
RISC_SPM/work/@r@i@s@c_@s@p@m/_primary.dat
RISC_SPM/work/@r@i@s@c_@s@p@m/verilog.asm
RISC_SPM/work/@r@i@s@c_@s@p@m/verilog.rw
RISC_SPM/work/@processing_@unit/_primary.vhd
RISC_SPM/work/@processing_@unit/_primary.dbs
RISC_SPM/work/@processing_@unit/_primary.dat
RISC_SPM/work/@processing_@unit/verilog.asm
RISC_SPM/work/@processing_@unit/verilog.rw
RISC_SPM/work/@register_@unit/_primary.vhd
RISC_SPM/work/@register_@unit/_primary.dbs
RISC_SPM/work/@register_@unit/_primary.dat
RISC_SPM/work/@register_@unit/verilog.asm
RISC_SPM/work/@register_@unit/verilog.rw
RISC_SPM/work/@d_flop/_primary.vhd
RISC_SPM/work/@d_flop/_primary.dbs
RISC_SPM/work/@d_flop/_primary.dat
RISC_SPM/work/@d_flop/verilog.asm
RISC_SPM/work/@d_flop/verilog.rw
RISC_SPM/work/@address_@register/_primary.vhd
RISC_SPM/work/@address_@register/_primary.dbs
RISC_SPM/work/@address_@register/_primary.dat
RISC_SPM/work/@address_@register/verilog.asm
RISC_SPM/work/@address_@register/verilog.rw
RISC_SPM/work/@instruction_@register/_primary.vhd
RISC_SPM/work/@instruction_@register/_primary.dbs
RISC_SPM/work/@instruction_@register/_primary.dat
RISC_SPM/work/@instruction_@register/verilog.asm
RISC_SPM/work/@instruction_@register/verilog.rw
RISC_SPM/work/@program_@counter/_primary.vhd
RISC_SPM/work/@program_@counter/_primary.dbs
RISC_SPM/work/@program_@counter/_primary.dat
RISC_SPM/work/@program_@counter/verilog.asm
RISC_SPM/work/@program_@counter/verilog.rw
RISC_SPM/work/@multiplexer_5ch/_primary.vhd
RISC_SPM/work/@multiplexer_5ch/_primary.dbs
RISC_SPM/work/@multiplexer_5ch/_primary.dat
RISC_SPM/work/@multiplexer_5ch/verilog.asm
RISC_SPM/work/@multiplexer_5ch/verilog.rw
RISC_SPM/work/@multiplexer_3ch/_primary.vhd
RISC_SPM/work/@multiplexer_3ch/_primary.dbs
RISC_SPM/work/@multiplexer_3ch/_primary.dat
RISC_SPM/work/@multiplexer_3ch/verilog.asm
RISC_SPM/work/@multiplexer_3ch/verilog.rw
RISC_SPM/work/@alu_@r@i@s@c/_primary.vhd
RISC_SPM/work/@alu_@r@i@s@c/_primary.dbs
RISC_SPM/work/@alu_@r@i@s@c/_primary.dat
RISC_SPM/work/@alu_@r@i@s@c/verilog.asm
RISC_SPM/work/@alu_@r@i@s@c/verilog.rw
RISC_SPM/work/@control_@unit/_primary.vhd
RISC_SPM/work/@control_@unit/_primary.dbs
RISC_SPM/work/@control_@unit/_primary.dat
RISC_SPM/work/@control_@unit/verilog.asm
RISC_SPM/work/@control_@unit/verilog.rw
RISC_SPM/work/@memory_@unit/_primary.vhd
RISC_SPM/work/@memory_@unit/_primary.dbs
RISC_SPM/work/@memory_@unit/_primary.dat
RISC_SPM/work/@memory_@unit/verilog.asm
RISC_SPM/work/@memory_@unit/verilog.rw
RISC_SPM/work/test_@r@i@s@c_@s@p@m/_primary.vhd
RISC_SPM/work/test_@r@i@s@c_@s@p@m/_primary.dbs
RISC_SPM/work/test_@r@i@s@c_@s@p@m/_primary.dat
RISC_SPM/work/test_@r@i@s@c_@s@p@m/verilog.asm
RISC_SPM/work/test_@r@i@s@c_@s@p@m/verilog.rw
RISC_SPM/work/@clock_@unit/_primary.vhd
RISC_SPM/work/@clock_@unit/_primary.dbs
RISC_SPM/work/@clock_@unit/_primary.dat
RISC_SPM/work/@clock_@unit/verilog.asm
RISC_SPM/work/@clock_@unit/verilog.rw
RISC_SPM/RISC_SPM.v
RISC_SPM/test_RISC_SPM.v
RISC_SPM/RISC_SPM.v.bak
RISC_SPM/Clock_Unit.v
RISC_SPM/vsim.wlf
RISC_SPM/test_RISC_SPM.v.bak
RISC_SPM/RISC_SPM.mpf
RISC_SPM/RISC_SPM.cr.mti
RISC_SPM/work/_temp
RISC_SPM/work/@r@i@s@c_@s@p@m
RISC_SPM/work/@processing_@unit
RISC_SPM/work/@register_@unit
RISC_SPM/work/@d_flop
RISC_SPM/work/@address_@register
RISC_SPM/work/@instruction_@register
RISC_SPM/work/@program_@counter
RISC_SPM/work/@multiplexer_5ch
RISC_SPM/work/@multiplexer_3ch
RISC_SPM/work/@alu_@r@i@s@c
RISC_SPM/work/@control_@unit
RISC_SPM/work/@memory_@unit
RISC_SPM/work/test_@r@i@s@c_@s@p@m
RISC_SPM/work/@clock_@unit
RISC_SPM/work
RISC_SPM
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