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文件名称:w11_latest[1].tar

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  • 上传时间:
    2012-11-16
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    697.83kb
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介绍说明--下载内容来自于网络,使用问题请自行百度

该项目包含一个完整的PDP - 11系统:一个内存管理单元七十○分之十一的CPU,但没有浮点单元,一组基本的单总线外围设备(DL11,LP11,PC11,RK11/RK05),以及最后但并非最不重要的一用于SRAM和PSRAM高速缓存和内存控制器。该设计的FPGA验证,目前运行Digilent的S3BOARD和NEXYS2板和靴子第5版的UNIX和2.11BSD UNIX操作系统。-The project contains a complete PDP-11 system: a 11/70 CPU with memory management unit, but without floating point unit, a basic set of UNIBUS peripherals (DL11, LP11, PC11, RK11/RK05), and last but not least a cache and memory controllers for SRAM and PSRAM. The design is FPGA proven, runs currently on Digilent S3BOARD and NEXYS2 boards and boots 5th Edition UNIX and 2.11BSD UNIX.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

w11/
w11/branches/
w11/tags/
w11/tags/w11a_V0.5/
w11/tags/w11a_V0.5/tools/
w11/tags/w11a_V0.5/tools/bin/
w11/tags/w11a_V0.5/tools/bin/telnet_wrapper
w11/tags/w11a_V0.5/tools/bin/tbw
w11/tags/w11a_V0.5/tools/bin/svn_set_ignore
w11/tags/w11a_V0.5/tools/bin/pi_rri
w11/tags/w11a_V0.5/tools/bin/xst_count_bels
w11/tags/w11a_V0.5/tools/bin/xilinx_vhdl_memcolltype_fix
w11/tags/w11a_V0.5/tools/bin/xilinx_ghdl_simprim
w11/tags/w11a_V0.5/tools/bin/xilinx_ghdl_unisim
w11/tags/w11a_V0.5/tools/bin/impact_wrapper
w11/tags/w11a_V0.5/tools/bin/set_ftdi_lat
w11/tags/w11a_V0.5/tools/bin/rm_dep
w11/tags/w11a_V0.5/tools/bin/tmuconv
w11/tags/w11a_V0.5/tools/bin/xilinx_vhdl_chop
w11/tags/w11a_V0.5/tools/bin/vbomconv
w11/tags/w11a_V0.5/tools/bin/telnet_starter
w11/tags/w11a_V0.5/tools/bin/xilinx_tsim_xon
w11/tags/w11a_V0.5/.cvsignore
w11/tags/w11a_V0.5/LICENSE_gpl_v2.txt
w11/tags/w11a_V0.5/COPYING.txt
w11/tags/w11a_V0.5/rtl/
w11/tags/w11a_V0.5/rtl/bplib/
w11/tags/w11a_V0.5/rtl/bplib/nexys2/
w11/tags/w11a_V0.5/rtl/bplib/nexys2/nexys2_pins.ucf
w11/tags/w11a_V0.5/rtl/bplib/nexys2/Makefile
w11/tags/w11a_V0.5/rtl/bplib/nexys2/n2_cram_dummy.vbom
w11/tags/w11a_V0.5/rtl/bplib/nexys2/tb/
w11/tags/w11a_V0.5/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd
w11/tags/w11a_V0.5/rtl/bplib/nexys2/tb/tb_nexys2_core.vhd
w11/tags/w11a_V0.5/rtl/bplib/nexys2/tb/tbw.dat
w11/tags/w11a_V0.5/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom
w11/tags/w11a_V0.5/rtl/bplib/nexys2/tb/.cvsignore
w11/tags/w11a_V0.5/rtl/bplib/nexys2/tb/Makefile
w11/tags/w11a_V0.5/rtl/bplib/nexys2/tb/tb_nexys2_core.vbom
w11/tags/w11a_V0.5/rtl/bplib/nexys2/n2_cram_dummy.vhd
w11/tags/w11a_V0.5/rtl/bplib/nexys2/n2_cram_memctl_as.vhd
w11/tags/w11a_V0.5/rtl/bplib/nexys2/nexys2lib.vhd
w11/tags/w11a_V0.5/rtl/bplib/nexys2/n2_cram_memctl_as.vbom
w11/tags/w11a_V0.5/rtl/bplib/nexys2/nexys2_pins_pmb0_rs232.ucf
w11/tags/w11a_V0.5/rtl/bplib/s3board/
w11/tags/w11a_V0.5/rtl/bplib/s3board/s3_humanio.vhd
w11/tags/w11a_V0.5/rtl/bplib/s3board/s3_dispdrv.vhd
w11/tags/w11a_V0.5/rtl/bplib/s3board/s3_rs232_iob_int.vbom
w11/tags/w11a_V0.5/rtl/bplib/s3board/s3_humanio.vbom
w11/tags/w11a_V0.5/rtl/bplib/s3board/s3boardlib.vbom
w11/tags/w11a_V0.5/rtl/bplib/s3board/s3_sram_memctl.vbom
w11/tags/w11a_V0.5/rtl/bplib/s3board/s3_rs232_iob_ext.vhd
w11/tags/w11a_V0.5/rtl/bplib/s3board/s3_rs232_iob_int_ext.vbom
w11/tags/w11a_V0.5/rtl/bplib/s3board/Makefile
w11/tags/w11a_V0.5/rtl/bplib/s3board/s3_humanio_rri.vbom
w11/tags/w11a_V0.5/rtl/bplib/s3board/s3_dispdrv.vbom
w11/tags/w11a_V0.5/rtl/bplib/s3board/s3_rs232_iob_int_ext.vhd
w11/tags/w11a_V0.5/rtl/bplib/s3board/tb/
w11/tags/w11a_V0.5/rtl/bplib/s3board/tb/tbw.dat
w11/tags/w11a_V0.5/rtl/bplib/s3board/tb/tb_s3board_fusp.vhd
w11/tags/w11a_V0.5/rtl/bplib/s3board/tb/.cvsignore
w11/tags/w11a_V0.5/rtl/bplib/s3board/tb/Makefile
w11/tags/w11a_V0.5/rtl/bplib/s3board/tb/tb_s3board_core.vbom
w11/tags/w11a_V0.5/rtl/bplib/s3board/tb/tb_s3board_fusp.vbom
w11/tags/w11a_V0.5/rtl/bplib/s3board/tb/tb_s3board_core.vhd
w11/tags/w11a_V0.5/rtl/bplib/s3board/s3_rs232_iob_int.vhd
w11/tags/w11a_V0.5/rtl/bplib/s3board/s3board_pins.ucf
w11/tags/w11a_V0.5/rtl/bplib/s3board/s3_humanio_rri.vhd
w11/tags/w11a_V0.5/rtl/bplib/s3board/s3_sram_memctl.vhd
w11/tags/w11a_V0.5/rtl/bplib/s3board/s3boardlib.vhd
w11/tags/w11a_V0.5/rtl/bplib/s3board/s3_rs232_iob_ext.vbom
w11/tags/w11a_V0.5/rtl/bplib/s3board/s3board_a2_pm1_rs232.ucf
w11/tags/w11a_V0.5/rtl/bplib/s3board/s3_sram_dummy.vbom
w11/tags/w11a_V0.5/rtl/bplib/s3board/s3_sram_dummy.vhd
w11/tags/w11a_V0.5/rtl/bplib/micron/
w11/tags/w11a_V0.5/rtl/bplib/micron/mt45w8mw16b.vhd
w11/tags/w11a_V0.5/rtl/bplib/micron/mt45w8mw16b.vbom
w11/tags/w11a_V0.5/rtl/bplib/issi/
w11/tags/w11a_V0.5/rtl/bplib/issi/is61lv25616al.vbom
w11/tags/w11a_V0.5/rtl/bplib/issi/Makefile
w11/tags/w11a_V0.5/rtl/bplib/issi/is61lv25616al.vhd
w11/tags/w11a_V0.5/rtl/vlib/
w11/tags/w11a_V0.5/rtl/vlib/memlib/
w11/tags/w11a_V0.5/rtl/vlib/memlib/ram_2swsr_xfirst_gen_unisim.vbom
w11/tags/w11a_V0.5/rtl/vlib/memlib/fifo_1c_dram.vbom
w11/tags/w11a_V0.5/rtl/vlib/memlib/memlib.vhd
w11/tags/w11a_V0.5/rtl/vlib/memlib/ram_1swar_1ar_gen_unisim.vhd
w11/tags/w11a_V0.5/rtl/vlib/memlib/ram_1swar_gen.vbom
w11/tags/w11a_V0.5/rtl/vlib/memlib/ram_1swar_gen_unisim.vhd
w11/tags/w11a_V0.5/rtl/vlib/memlib/ram_1swar_gen.vhd
w11/tags/w11a_V0.5/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vbom
w11/tags/w11a_V0.5/rtl/vlib/memlib/fifo_1c_dram_raw.vbom
w11/tags/w11a_V0.5/rtl/vlib/memlib/Makefile
w11/tags/w11a_V0.5/rtl/vlib/memlib/ram_2swsr_xfirst_gen_unisim.vhd
w11/tags/w11a_V0.5/rtl/vlib/memlib/ram_2swsr_rfirst_gen_unisim.vbom
w11/tags/w11a_V0.5/rtl/vlib/memlib/ram_1swar_1ar_gen_unisim.vbom
w11/tags/w11a_V0.5/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd
w11/tags/w11a_V0.5/rtl/vlib/memlib/ram_2swsr_rfirst_gen_unisim.vhd
w11/tags/w11a_V0.5/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd
w11/tags/w11a_V0.5/rtl/vlib/memlib/fifo_1c_dram_raw.vhd
w11/tags/w11a_V0.5/rtl/vlib/memlib/ram_1swar_1ar_gen.vbom
w11/tags/w11a_V0.5/rtl/vlib/memlib/fifo_1c_dram.vhd
w11/tags/w11a_V0.5/rtl/vlib/memlib/ram_1swar_gen_unisim.vbom
w11/tags/w11a_V0.5/rtl/vlib/genlib/
w11/tags/w11a_V0.5/rtl/vlib/genlib/clkdivce.

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