CDN加速镜像 | 设为首页 | 加入收藏夹
登陆 | 会员注册
当前位置： 首页 资源下载 源码下载 嵌入式/单片机编程 VHDL编程
收藏

文件名称:ddr3_altera_use

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    11.11mb
  • 已下载：
    0次
  • 提 供 者：
    dido*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

altera kit gx4 上DDR3 控制器的使用-altera kit gx4 on the use of DDR3 controller
(系统自动生成,下载前可以参看下载内容)

下载文件列表

ddr3_bts_GUI_C2ES_sp1/alt_mem_phy_defines.v
ddr3_bts_GUI_C2ES_sp1/altera/
ddr3_bts_GUI_C2ES_sp1/altera/90/
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/primitives/
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/primitives/altera_avalon_st_clock_crosser/
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/primitives/altera_avalon_st_clock_crosser/altera_avalon_st_clock_crosser.v
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/primitives/altera_avalon_st_pipeline_stage/
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/primitives/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_stage.v
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/sopc_builder_ip/
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/sopc_builder_ip/altera_avalon_jtag_phy/
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/sopc_builder_ip/altera_avalon_jtag_phy/altera_avalon_st_jtag_interface.v
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/sopc_builder_ip/altera_avalon_jtag_phy/altera_jtag_dc_streaming.v
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/sopc_builder_ip/altera_avalon_jtag_phy/altera_jtag_phy.v
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/sopc_builder_ip/altera_avalon_jtag_phy/altera_jtag_streaming.v
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/sopc_builder_ip/altera_avalon_jtag_phy/altera_pli_streaming.v
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/sopc_builder_ip/altera_avalon_packets_to_master/
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/sopc_builder_ip/altera_avalon_packets_to_master/altera_avalon_packets_to_master.v
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo.v
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/sopc_builder_ip/altera_avalon_st_bytes_to_packets/
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/sopc_builder_ip/altera_avalon_st_bytes_to_packets/altera_avalon_st_bytes_to_packets.v
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/sopc_builder_ip/altera_avalon_st_idle_inserter/
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/sopc_builder_ip/altera_avalon_st_idle_inserter/altera_avalon_st_idle_inserter.v
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/sopc_builder_ip/altera_avalon_st_idle_remover/
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/sopc_builder_ip/altera_avalon_st_idle_remover/altera_avalon_st_idle_remover.v
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/sopc_builder_ip/altera_avalon_st_packets_to_bytes/
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/sopc_builder_ip/altera_avalon_st_packets_to_bytes/altera_avalon_st_packets_to_bytes.v
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/sopc_builder_ip/altera_jtag_avalon_master/
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/sopc_builder_ip/altera_jtag_avalon_master/altera_jtag_avalon_master.v
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/sopc_builder_ip/altera_jtag_avalon_master/altera_jtag_avalon_master_common_modules.v
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/sopc_builder_ip/altera_jtag_avalon_master/altera_jtag_avalon_master_hw.tcl
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/sopc_builder_ip/altera_jtag_avalon_master/altera_jtag_avalon_master_pli_off.v
ddr3_bts_GUI_C2ES_sp1/altera/90/ip/altera/sopc_builder_ip/altera_jtag_avalon_master/altera_jtag_avalon_master_pli_on.v
ddr3_bts_GUI_C2ES_sp1/altmemphy-library/
ddr3_bts_GUI_C2ES_sp1/altmemphy-library/auk_ddr3_hp_controller.ocp
ddr3_bts_GUI_C2ES_sp1/altpllpll_0.bsf
ddr3_bts_GUI_C2ES_sp1/altpllpll_0.ppf
ddr3_bts_GUI_C2ES_sp1/altpllpll_0.qip
ddr3_bts_GUI_C2ES_sp1/altpllpll_0.v
ddr3_bts_GUI_C2ES_sp1/altpllpll_0_bb.v
ddr3_bts_GUI_C2ES_sp1/assignment_defaults.qdf
ddr3_bts_GUI_C2ES_sp1/auk_ddr3_hp_controller.ocp
ddr3_bts_GUI_C2ES_sp1/auk_ddr3_hp_controller.vhd
ddr3_bts_GUI_C2ES_sp1/Copy of ddr3_bot.out.sdc
ddr3_bts_GUI_C2ES_sp1/cpu_0.sdc
ddr3_bts_GUI_C2ES_sp1/cpu_0.v
ddr3_bts_GUI_C2ES_sp1/cpu_0_bht_ram.mif
ddr3_bts_GUI_C2ES_sp1/cpu_0_dc_tag_ram.mif
ddr3_bts_GUI_C2ES_sp1/cpu_0_ic_tag_ram.mif
ddr3_bts_GUI_C2ES_sp1/cpu_0_jtag_debug_module_sysclk.v
ddr3_bts_GUI_C2ES_sp1/cpu_0_jtag_debug_module_tck.v
ddr3_bts_GUI_C2ES_sp1/cpu_0_jtag_debug_module_wrapper.v
ddr3_bts_GUI_C2ES_sp1/cpu_0_mult_cell.v
ddr3_bts_GUI_C2ES_sp1/cpu_0_oci_test_bench.v
ddr3_bts_GUI_C2ES_sp1/cpu_0_ociram_default_contents.mif
ddr3_bts_GUI_C2ES_sp1/cpu_0_rf_ram_a.mif
ddr3_bts_GUI_C2ES_sp1/cpu_0_rf_ram_b.mif
ddr3_bts_GUI_C2ES_sp1/cpu_0_test_bench.v
ddr3_bts_GUI_C2ES_sp1/ddr3_bot.archive.rpt
ddr3_bts_GUI_C2ES_sp1/ddr3_bot.asm.rpt
ddr3_bts_GUI_C2ES_sp1/ddr3_bot.cbx.xml
ddr3_bts_GUI_C2ES_sp1/ddr3_bot.cdf
ddr3_bts_GUI_C2ES_sp1/ddr3_bot.done
ddr3_bts_GUI_C2ES_sp1/ddr3_bot.dpf
ddr3_bts_GUI_C2ES_sp1/ddr3_bot.fit.rpt
ddr3_bts_GUI_C2ES_sp1/ddr3_bot.fit.smsg
ddr3_bts_GUI_C2ES_sp1/ddr3_bot.fit.summary
ddr3_bts_GUI_C2ES_sp1/ddr3_bot.flow.rpt
ddr3_bts_GUI_C2ES_sp1/ddr3_bot.jdi
ddr3_bts_GUI_C2ES_sp1/ddr3_bot.map.rpt
ddr3_bts_GUI_C2ES_sp1/ddr3_bot.map.smsg
ddr3_bts_GUI_C2ES_sp1/ddr3_bot.map.summary
ddr3_bts_GUI_C2ES_sp1/ddr3_bot.merge.rpt
ddr3_bts_GUI_C2ES_sp1/ddr3_bot.mif_update.rpt
ddr3_bts_GUI_C2ES_sp1/ddr3_bot.out.sdc
ddr3_bts_GUI_C2ES_sp1/ddr3_bot.pin
ddr3_bts_GUI_C2ES_sp1/ddr3_bot.qarlog
ddr3_bts_G

相关说明

  • 本站资源为会员上传分享交流与学习,如有侵犯您的权益,请联系我们删除.
  • 搜珍网是交换下载平台，只提供交流渠道，下载内容来自于网络，除下载问题外，其它问题请自行百度。更多...
  • 本站已设置防盗链，请勿用迅雷、QQ旋风等下载软件下载资源，下载后用WinRAR最新版进行解压.
  • 如果您发现内容无法下载，请稍后再次尝试；或换浏览器；或者到消费记录里找到下载记录反馈给我们.
  • 下载后发现下载的内容跟说明不相乎，请到消费记录里找到下载记录反馈给我们，经确认后退回积分.
  • 如下载前有疑问，可以通过点击"提供者"的名字，查看对方的联系方式，联系对方咨询.
查看所有评论

相关评论

暂无评论内容．

发表评论

*快速评论： 推荐 一般 有密码 和说明不符 不是源码或资料 文件不全 不能解压 纯粹是垃圾
*内　　容：
*验 证 码：
搜珍网 www.dssz.com