CDN加速镜像 | 设为首页 | 加入收藏夹
当前位置: 首页 资源下载 源码下载 嵌入式/单片机编程 VHDL编程

文件名称:sdr-sdram-(verilog)

  • 所属分类:
  • 标签属性:
  • 上传时间:
    2012-11-16
  • 文件大小:
    759.18kb
  • 已下载:
    1次
  • 提 供 者:
  • 相关连接:
  • 下载说明:
    别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容来自于网络,使用问题请自行百度

Altera的SDR SDRAM模型,verilog实现,带说明书文件以及仿真文件、SDRAM原型文件。-Altera' s SDR SDRAM model, verilog implementation, with manual files and simulation files, SDRAM prototype file.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

verilog
verilog/doc
verilog/doc/readme.txt
verilog/doc/sdr_sdram.pdf
verilog/model
verilog/model/mt48lc8m16a2.v
verilog/route
verilog/route/PLL1.v
verilog/route/sdr_sdram.csf
verilog/route/sdr_sdram.esf
verilog/route/sdr_sdram.vqm
verilog/simulation
verilog/simulation/modelsim.ini
verilog/simulation/readme.txt
verilog/simulation/sdr_sdram_tb.v
verilog/simulation/work
verilog/simulation/work/altclklock
verilog/simulation/work/altclklock/verilog.psm
verilog/simulation/work/altclklock/_primary.dat
verilog/simulation/work/altclklock/_primary.vhd
verilog/simulation/work/command
verilog/simulation/work/command/verilog.psm
verilog/simulation/work/command/_primary.dat
verilog/simulation/work/command/_primary.vhd
verilog/simulation/work/control_interface
verilog/simulation/work/control_interface/verilog.psm
verilog/simulation/work/control_interface/_primary.dat
verilog/simulation/work/control_interface/_primary.vhd
verilog/simulation/work/mt48lc8m16a2
verilog/simulation/work/mt48lc8m16a2/verilog.psm
verilog/simulation/work/mt48lc8m16a2/_primary.dat
verilog/simulation/work/mt48lc8m16a2/_primary.vhd
verilog/simulation/work/pll1
verilog/simulation/work/pll1/verilog.psm
verilog/simulation/work/pll1/_primary.dat
verilog/simulation/work/pll1/_primary.vhd
verilog/simulation/work/sdr_data_path
verilog/simulation/work/sdr_data_path/verilog.psm
verilog/simulation/work/sdr_data_path/_primary.dat
verilog/simulation/work/sdr_data_path/_primary.vhd
verilog/simulation/work/sdr_sdram
verilog/simulation/work/sdr_sdram/verilog.psm
verilog/simulation/work/sdr_sdram/_primary.dat
verilog/simulation/work/sdr_sdram/_primary.vhd
verilog/simulation/work/sdr_sdram_tb
verilog/simulation/work/sdr_sdram_tb/verilog.psm
verilog/simulation/work/sdr_sdram_tb/_primary.dat
verilog/simulation/work/sdr_sdram_tb/_primary.vhd
verilog/simulation/work/_info
verilog/source
verilog/source/altclklock.v
verilog/source/Command.v
verilog/source/compile_all.v
verilog/source/control_interface.v
verilog/source/Params.v
verilog/source/PLL1.v
verilog/source/sdr_data_path.v
verilog/source/sdr_sdram.v
verilog/synthesis
verilog/synthesis/synplicity
verilog/synthesis/synplicity/sdr_sdram.prj

相关说明

  • 本站资源为会员上传分享交流与学习,如有侵犯您的权益,请联系我们删除.
  • 搜珍网是交换下载平台,只提供交流渠道,下载内容来自于网络,除下载问题外,其它问题请自行百度。更多...
  • 本站已设置防盗链,请勿用迅雷、QQ旋风等下载软件下载资源,下载后用WinRAR最新版进行解压.
  • 如果您发现内容无法下载,请稍后再次尝试;或换浏览器;或者到消费记录里找到下载记录反馈给我们.
  • 下载后发现下载的内容跟说明不相乎,请到消费记录里找到下载记录反馈给我们,经确认后退回积分.
  • 如下载前有疑问,可以通过点击"提供者"的名字,查看对方的联系方式,联系对方咨询.

相关评论

暂无评论内容.

发表评论

*快速评论: 推荐 一般 有密码 和说明不符 不是源码或资料 文件不全 不能解压 纯粹是垃圾
*内  容:
*验 证 码:
搜珍网 www.dssz.com