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文件名称:double_dcm

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  • 上传时间:
    2012-11-16
  • 文件大小:
    79.21kb
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介绍说明--下载内容来自于网络,使用问题请自行百度

这个主要是在xilinx FPGA中双DCM连接的问题,这个问题网上资料很少,自己研究后并且仿真之后可以实现两个dcm的正常工作,实现倍频和时钟的反相-This is mainly the double in xilinx FPGA DCM connection problem which little information online, their own studies and simulation can be achieved after the normal work of the two dcm achieve clock frequency and the inverse
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下载文件列表

double_dcm/coregen.cgc
double_dcm/coregen.cgp
double_dcm/dcm1.v
double_dcm/dcm1_arwz.ucf
double_dcm/dcm1_summary.html
double_dcm/dcm2.v
double_dcm/dcm2_arwz.ucf
double_dcm/double_dcm.gise
double_dcm/double_dcm.xise
double_dcm/ipcore_dir/dcm1.cgc
double_dcm/ipcore_dir/dcm1.cgp
double_dcm/ipcore_dir/dcm1.v
double_dcm/ipcore_dir/dcm1.xaw
double_dcm/ipcore_dir/dcm1_arwz.ucf
double_dcm/ipcore_dir/dcm1_flist.txt
double_dcm/ipcore_dir/dcm1_readme.txt
double_dcm/ipcore_dir/dcm1_xmdf.tcl
double_dcm/ipcore_dir/dcm2.cgc
double_dcm/ipcore_dir/dcm2.cgp
double_dcm/ipcore_dir/dcm2.v
double_dcm/ipcore_dir/dcm2.xaw
double_dcm/ipcore_dir/dcm2_arwz.ucf
double_dcm/ipcore_dir/dcm2_flist.txt
double_dcm/ipcore_dir/dcm2_readme.txt
double_dcm/ipcore_dir/dcm2_xmdf.tcl
double_dcm/ipcore_dir/xaw2verilog.log
double_dcm/iseconfig/dcm1.xreport
double_dcm/iseconfig/double_dcm.projectmgr
double_dcm/modelsim.ini
double_dcm/readme.txt
double_dcm/top.v
double_dcm/top_sim.fdo
double_dcm/top_sim.udo
double_dcm/top_sim.v
double_dcm/top_sim_summary.html
double_dcm/top_sim_wave.fdo
double_dcm/transcript
double_dcm/vsim.wlf
double_dcm/work/dcm1/verilog.asm
double_dcm/work/dcm1/verilog.rw
double_dcm/work/dcm1/_primary.dat
double_dcm/work/dcm1/_primary.dbs
double_dcm/work/dcm1/_primary.vhd
double_dcm/work/dcm2/verilog.asm
double_dcm/work/dcm2/verilog.rw
double_dcm/work/dcm2/_primary.dat
double_dcm/work/dcm2/_primary.dbs
double_dcm/work/dcm2/_primary.vhd
double_dcm/work/glbl/verilog.asm
double_dcm/work/glbl/verilog.rw
double_dcm/work/glbl/_primary.dat
double_dcm/work/glbl/_primary.dbs
double_dcm/work/glbl/_primary.vhd
double_dcm/work/top/verilog.asm
double_dcm/work/top/verilog.rw
double_dcm/work/top/_primary.dat
double_dcm/work/top/_primary.dbs
double_dcm/work/top/_primary.vhd
double_dcm/work/top_sim/verilog.asm
double_dcm/work/top_sim/verilog.rw
double_dcm/work/top_sim/_primary.dat
double_dcm/work/top_sim/_primary.dbs
double_dcm/work/top_sim/_primary.vhd
double_dcm/work/_info
double_dcm/work/_vmake
double_dcm/xaw2verilog.log
double_dcm/_xmsgs/pn_parser.xmsgs
double_dcm/ipcore_dir/tmp/_cg
double_dcm/ipcore_dir/tmp
double_dcm/work/dcm1
double_dcm/work/dcm2
double_dcm/work/glbl
double_dcm/work/top
double_dcm/work/top_sim
double_dcm/work/_temp
double_dcm/ipcore_dir
double_dcm/iseconfig
double_dcm/work
double_dcm/_xmsgs
double_dcm

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