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文件名称:ddsfinal1

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    2012-11-16
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    1.09mb
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verilog语言实现的dds代码,并行通信,生成四种波形,大赛编写的代码,modelsim仿真-verilog language dds code,modelsim debug
(系统自动生成,下载前可以参看下载内容)

下载文件列表

ddsfinal1/rom_syn.v
ddsfinal1/dds_final.v
ddsfinal1/nmux4.v
ddsfinal1/decoder_38.v
ddsfinal1/dds.v
ddsfinal1/rom.mif
ddsfinal1/dds_final.qpf
ddsfinal1/dds_final.qsf
ddsfinal1/dds_final.map.summary
ddsfinal1/dds_final.pin
ddsfinal1/dds_final.fit.smsg
ddsfinal1/dds_final.fit.summary
ddsfinal1/dds_final.sof
ddsfinal1/dds_final.pof
ddsfinal1/dds_final.tan.summary
ddsfinal1/dds_final.v.bak
ddsfinal1/dds_final.merge.rpt
ddsfinal1/dds_final.done
ddsfinal1/dds_final_nativelink_simulation.rpt
ddsfinal1/rom_syn_waveforms.html
ddsfinal1/rom_syn_wave0.jpg
ddsfinal1/rom_syn_wave1.jpg
ddsfinal1/rom_syn.inc
ddsfinal1/rom_syn.bsf
ddsfinal1/rom_syn_inst.v
ddsfinal1/rom_syn_bb.v
ddsfinal1/rom_syn.qip
ddsfinal1/dds.bsf
ddsfinal1/dds_final.bsf
ddsfinal1/decoder_38.bsf
ddsfinal1/nmux4.bsf
ddsfinal1/dds_final.dpf
ddsfinal1/dds_final.cdf
ddsfinal1/simulation/modelsim/dds_final_modelsim.xrf
ddsfinal1/simulation/modelsim/dds_final.vo
ddsfinal1/simulation/modelsim/dds_final_v.sdo
ddsfinal1/simulation/modelsim/dds_final_run_msim_rtl_verilog.do.bak2
ddsfinal1/simulation/modelsim/dds_final_run_msim_rtl_verilog.do
ddsfinal1/simulation/modelsim/dds_final_run_msim_rtl_verilog.do.bak3
ddsfinal1/simulation/modelsim/dds_final_run_msim_rtl_verilog.do.bak4
ddsfinal1/simulation/modelsim/vsim.wlf
ddsfinal1/simulation/modelsim/rom.mif
ddsfinal1/simulation/modelsim/rom.ver
ddsfinal1/simulation/modelsim/dds_final_run_msim_rtl_verilog.do.bak
ddsfinal1/simulation/modelsim/dds_final_run_msim_rtl_verilog.do.bak1
ddsfinal1/simulation/modelsim/dds_final.vt.bak
ddsfinal1/simulation/modelsim/dds_final.vt
ddsfinal1/simulation/modelsim/dds_final_run_msim_rtl_verilog.do.bak5
ddsfinal1/simulation/modelsim/dds_final.sft
ddsfinal1/simulation/modelsim/dds_final_run_msim_rtl_verilog.do.bak6
ddsfinal1/simulation/modelsim/msim_transcript
ddsfinal1/simulation/modelsim/rtl_work/_info
ddsfinal1/simulation/modelsim/rtl_work/_vmake
ddsfinal1/simulation/modelsim/rtl_work/rom_syn/_primary.vhd
ddsfinal1/simulation/modelsim/rtl_work/rom_syn/verilog.psm
ddsfinal1/simulation/modelsim/rtl_work/rom_syn/_primary.dbs
ddsfinal1/simulation/modelsim/rtl_work/rom_syn/_primary.dat
ddsfinal1/simulation/modelsim/rtl_work/dds/_primary.vhd
ddsfinal1/simulation/modelsim/rtl_work/dds/verilog.psm
ddsfinal1/simulation/modelsim/rtl_work/dds/_primary.dbs
ddsfinal1/simulation/modelsim/rtl_work/dds/_primary.dat
ddsfinal1/simulation/modelsim/rtl_work/dds_final/_primary.vhd
ddsfinal1/simulation/modelsim/rtl_work/dds_final/verilog.psm
ddsfinal1/simulation/modelsim/rtl_work/dds_final/_primary.dbs
ddsfinal1/simulation/modelsim/rtl_work/dds_final/_primary.dat
ddsfinal1/simulation/modelsim/rtl_work/decoder_38/_primary.vhd
ddsfinal1/simulation/modelsim/rtl_work/decoder_38/verilog.psm
ddsfinal1/simulation/modelsim/rtl_work/decoder_38/_primary.dbs
ddsfinal1/simulation/modelsim/rtl_work/decoder_38/_primary.dat
ddsfinal1/simulation/modelsim/rtl_work/nmux4/_primary.vhd
ddsfinal1/simulation/modelsim/rtl_work/nmux4/verilog.psm
ddsfinal1/simulation/modelsim/rtl_work/nmux4/_primary.dbs
ddsfinal1/simulation/modelsim/rtl_work/nmux4/_primary.dat
ddsfinal1/simulation/modelsim/rtl_work/dds_final_vlg_tst/_primary.vhd
ddsfinal1/simulation/modelsim/rtl_work/dds_final_vlg_tst/verilog.psm
ddsfinal1/simulation/modelsim/rtl_work/dds_final_vlg_tst/_primary.dbs
ddsfinal1/simulation/modelsim/rtl_work/dds_final_vlg_tst/_primary.dat
ddsfinal1/simulation/modelsim/modelsim.ini
ddsfinal1/incremental_db/README
ddsfinal1/incremental_db/compiled_partitions/dds_final.root_partition.map.kpt
ddsfinal1/incremental_db/compiled_partitions/dds_final.root_partition.map.atm
ddsfinal1/incremental_db/compiled_partitions/dds_final.root_partition.map.hdbx
ddsfinal1/incremental_db/compiled_partitions/dds_final.root_partition.cmp.rcf
ddsfinal1/incremental_db/compiled_partitions/dds_final.root_partition.cmp.hdbx
ddsfinal1/incremental_db/compiled_partitions/dds_final.root_partition.cmp.atm
ddsfinal1/incremental_db/compiled_partitions/dds_final.root_partition.cmp.logdb
ddsfinal1/incremental_db/compiled_partitions/dds_final.root_partition.cmp.kpt
ddsfinal1/incremental_db/compiled_partitions/dds_final.root_partition.map.dpi
ddsfinal1/incremental_db/compiled_partitions/dds_final.root_partition.cmp.dfp
ddsfinal1/db/dds_final.db_info
ddsfinal1/db/prev_cmp_dds_final.qmsg
ddsfinal1/db/dds_final.eda.qmsg
ddsfinal1/db/dds_final.lpc.html
ddsfinal1/db/dds_final.cmp.cdb
ddsfinal1/db/dds_final.tis_db_list.ddb
ddsfinal1/db/dds_final.cbx.xml
ddsfinal1/db/dds_final.hif
ddsfinal1/db/dds_final.lpc.rdb
ddsfinal1/db/dds_final.(1).cnf.cdb
ddsfinal1/db/dds_final.(1).cnf.hdb
ddsfinal1/db/dds_final.(2).cnf.cdb
ddsfinal1/db/dds_final.(2).cnf.hdb
ddsfinal1/db/dds_final.(3).cnf.cdb
ddsfinal1/db/dds_final.(3).cnf.hdb
ddsfinal1/db/dds_final.(4).cnf.cdb
ddsfinal1/db/dds_final.(4).cnf.hdb
ddsfinal1/db/altsyncram_qa91.tdf
ddsfinal1/db/dds_final.(5).cnf.cdb
ddsfinal1/db/dds_final.(5).cnf.hdb
ddsfinal1/db/dds_final.(6).cnf.cdb
ddsfinal1/db/dds_final.(6).cnf.hdb
ddsfinal1/db/dds_final.hier_info
ddsfinal1/db/dds_final.pre_map.hdb
ddsfinal1/db/dds_final.pre_map.cdb
ddsfinal1/db/dds_final.rpp.qmsg
ddsfinal1/d

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