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文件名称:mycpri

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    2012-11-16
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    1.33mb
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CPRI:采用数字的方式来传输基带信号,其数字接口有两种,标准的CPRI和OBSAI接口。CPRI(The Common Public Radio Interface)定义了基站数据处理控制单元REC(Radio Equipment Control)与基站收发单元RE(Radio Equipment)之间的接口关系,它的数据结构可以直接用于直放站的数据进行远端传输,成为基站的一种拉远系统。-CPRI IP core xilinx examples
相关搜索: cpri 基带信号

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下载文件列表

mycpri/cpri_readme.txt
mycpri/doc/cpri_ds611.pdf
mycpri/doc/cpri_gsg446.pdf
mycpri/doc/cpri_ug447.pdf
mycpri/example_design/cpri_block.vhd
mycpri/example_design/cpri_example.ucf
mycpri/example_design/cpri_example.vhd
mycpri/example_design/gtp_and_clocks/gtp/rocketio_wrapper.vhd
mycpri/example_design/gtp_and_clocks/gtp/rocketio_wrapper_tile.vhd
mycpri/example_design/gtp_and_clocks/gtp/rx_sync.vhd
mycpri/example_design/gtp_and_clocks/gtp/tx_sync.vhd
mycpri/example_design/gtp_and_clocks/gtp0_speed_controller.vhd
mycpri/example_design/gtp_and_clocks/gtp1_speed_controller.vhd
mycpri/example_design/gtp_and_clocks/gtp_and_clocks.vhd
mycpri/example_design/gtp_and_clocks/rx_clk_gen.vhd
mycpri/example_design/gtp_and_clocks/rx_dcm_speed_controller.vhd
mycpri/example_design/gtp_and_clocks/tx_clk_gen.vhd
mycpri/example_design/gtp_and_clocks/tx_pll_speed_controller.vhd
mycpri/hdl/cdc.vhd
mycpri/hdl/cdc_average.vhd
mycpri/hdl/cdc_count.vhd
mycpri/hdl/cdc_fifo.vhd
mycpri/hdl/cdc_fifo_pack.vhd
mycpri/hdl/cdc_handshake.vhd
mycpri/hdl/cpri.vhd
mycpri/hdl/cpri_pack.vhd
mycpri/hdl/ethernet_fifo/ethfifo.ngc
mycpri/hdl/ethernet_fifo/ethfifo.vhd
mycpri/hdl/ethernet_fifo/ethfifo.xco
mycpri/hdl/ethernet_fifo/ethfifo_struct.vhd
mycpri/hdl/eth_decode_5b_pack.vhd
mycpri/hdl/eth_encode_5b_pack.vhd
mycpri/hdl/line_rate_manager.vhd
mycpri/hdl/mgmnt.vhd
mycpri/hdl/picoblaze/cpri_rom.psm
mycpri/hdl/picoblaze/cpri_rom.vhd
mycpri/hdl/picoblaze/embedded_kcpsm3.vhd
mycpri/hdl/picoblaze/kcpsm3.vhd
mycpri/hdl/pulse_gen.vhd
mycpri/hdl/r21_timer_counter.vhd
mycpri/hdl/reset_synchronizer.vhd
mycpri/hdl/rx_cw_memory.vhd
mycpri/hdl/rx_ethernet.vhd
mycpri/hdl/rx_eth_cpri.vhd
mycpri/hdl/rx_eth_mii.vhd
mycpri/hdl/rx_framing.vhd
mycpri/hdl/rx_hdlc.vhd
mycpri/hdl/rx_hfnsync.vhd
mycpri/hdl/rx_iq.vhd
mycpri/hdl/rx_modules.vhd
mycpri/hdl/shift_reg.vhd
mycpri/hdl/synchronizer.vhd
mycpri/hdl/toggle_detect.vhd
mycpri/hdl/tx_ctrl.vhd
mycpri/hdl/tx_ethernet.vhd
mycpri/hdl/tx_eth_cpri.vhd
mycpri/hdl/tx_eth_mii.vhd
mycpri/hdl/tx_framing.vhd
mycpri/hdl/tx_hdlc.vhd
mycpri/hdl/tx_iq.vhd
mycpri/hdl/tx_modules.vhd
mycpri/hdl/tx_mux.vhd
mycpri/implement/cpri_example.prj
mycpri/implement/cpri_example.scr
mycpri/implement/implement.bat
mycpri/implement/implement.sh
mycpri/simulation/cpri_harness.vhd
mycpri/simulation/cpri_harness_alarm_tb.vhd
mycpri/simulation/cpri_harness_hdlc_tb.vhd
mycpri/simulation/cpri_harness_iqeth_tb.vhd
mycpri/simulation/cpri_harness_passive_tb.vhd
mycpri/simulation/cpri_tb_pkg.vhd
mycpri/simulation/cpri_test.tcl
mycpri/simulation/demo_tb.vhd
mycpri/simulation/eth_tx_gen.vhd
mycpri/simulation/functional/simulate_mti.do
mycpri/simulation/functional/wave_mti.do
mycpri/simulation/testcases/alarm-2.do
mycpri/simulation/testcases/hdlc-0_240.do
mycpri/simulation/testcases/hdlc-0_480.do
mycpri/simulation/testcases/hdlc-1_960.do
mycpri/simulation/testcases/hdlc-2_1920.do
mycpri/simulation/testcases/iqeth-0.do
mycpri/simulation/testcases/iqeth-1.do
mycpri/simulation/testcases/iqeth-2.do
mycpri/simulation/testcases/iqeth-3.do
mycpri/simulation/testcases/iqeth-4.do
mycpri/simulation/testcases/iqeth-5.do
mycpri/simulation/testcases/iqeth-col.do
mycpri/simulation/testcases/passive-0.do
mycpri/simulation/testcases/wave_alarm_mti.do
mycpri/simulation/testcases/wave_hdlc_mti.do
mycpri/simulation/testcases/wave_iqeth_mti.do
mycpri/simulation/testcases/wave_passive_mti.do
mycpri/example_design/gtp_and_clocks/gtp
mycpri/example_design/gtp_and_clocks
mycpri/hdl/ethernet_fifo
mycpri/hdl/picoblaze
mycpri/simulation/functional
mycpri/simulation/testcases
mycpri/doc
mycpri/example_design
mycpri/hdl
mycpri/implement
mycpri/simulation
mycpri

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