用VHDL 语言设计数字钟，实现在数码管上显示分钟和秒，并且可以手动调节分钟，

实现分钟的增或者减。该设计包括以下几个部分：

（1）分频电路的设计，产生1Hz 的时钟信号，作为秒计时脉冲；

（2）手动调节电路，包括“时增”“时减”“分增”“分减”。

（3）时分秒计时电路。

（4）7 段数码管显示电路。-Design with VHDL, digital clock, to achieve in the digital display minutes and seconds, and you can manually adjust the minutes, to achieve the increase or decrease minutes. The design includes the following sections: (1) frequency circuit design, produce 1Hz clock signal, as the second timing pulse　(2) Manual adjustment circuit, including " the increase"　" decrease the time"　" point by"　" sub- less. "　(3), minute and second timing circuits. (4) 7-segment display circuit.