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文件名称:lab1

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    2012-11-16
  • 文件大小:
    4.51mb
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xilinx官网edk实验,lab1,用nexys 2 板实验源代码-xilinx edk official website experiments, lab1, with nexys 2 plate test source code
(系统自动生成,下载前可以参看下载内容)

下载文件列表

lab1/
lab1/bitinit.log
lab1/blkdiagram/
lab1/blkdiagram/svg10.dtd
lab1/blkdiagram/system.css
lab1/blkdiagram/system.html
lab1/blkdiagram/system.svg
lab1/clock_generator_0.log
lab1/data/
lab1/data/system.ucf
lab1/etc/
lab1/etc/bitgen.ut
lab1/etc/download.cmd
lab1/etc/fast_runtime.opt
lab1/hdl/
lab1/hdl/clock_generator_0_wrapper.vhd
lab1/hdl/debug_module_wrapper.vhd
lab1/hdl/dlmb_cntlr_wrapper.vhd
lab1/hdl/dlmb_wrapper.vhd
lab1/hdl/elaborate/
lab1/hdl/elaborate/lmb_bram_elaborate_v1_00_a/
lab1/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/
lab1/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/
lab1/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/lmb_bram_elaborate.vhd
lab1/hdl/ilmb_cntlr_wrapper.vhd
lab1/hdl/ilmb_wrapper.vhd
lab1/hdl/lmb_bram_wrapper.vhd
lab1/hdl/mb_plb_wrapper.vhd
lab1/hdl/microblaze_0_wrapper.vhd
lab1/hdl/micron_ram_util_bus_split_0_wrapper.vhd
lab1/hdl/micron_ram_wrapper.vhd
lab1/hdl/proc_sys_reset_0_wrapper.vhd
lab1/hdl/rs232_port_wrapper.vhd
lab1/hdl/system.vhd
lab1/hdl/system_stub.vhd
lab1/implementation/
lab1/implementation/bitgen.ut
lab1/implementation/cache/
lab1/implementation/cache/cache.cat
lab1/implementation/cache/clock_generator_0_wrapper.ngc
lab1/implementation/cache/debug_module_wrapper.ngc
lab1/implementation/cache/dlmb_cntlr_wrapper.ngc
lab1/implementation/cache/dlmb_wrapper.ngc
lab1/implementation/cache/ilmb_cntlr_wrapper.ngc
lab1/implementation/cache/ilmb_wrapper.ngc
lab1/implementation/cache/lmb_bram_wrapper.ngc
lab1/implementation/cache/mb_plb_wrapper.ngc
lab1/implementation/cache/microblaze_0_wrapper.ngc
lab1/implementation/cache/micron_ram_util_bus_split_0_wrapper.ngc
lab1/implementation/cache/micron_ram_wrapper.ngc
lab1/implementation/cache/proc_sys_reset_0_wrapper.ngc
lab1/implementation/cache/rs232_port_wrapper.ngc
lab1/implementation/clock_generator_0_wrapper/
lab1/implementation/clock_generator_0_wrapper.ngc
lab1/implementation/clock_generator_0_wrapper.ngc_xst.xrpt
lab1/implementation/clock_generator_0_wrapper_vhdl.prj
lab1/implementation/debug_module_wrapper/
lab1/implementation/debug_module_wrapper.ngc
lab1/implementation/debug_module_wrapper.ngc_xst.xrpt
lab1/implementation/debug_module_wrapper_vhdl.prj
lab1/implementation/dlmb_cntlr_wrapper/
lab1/implementation/dlmb_cntlr_wrapper.ngc
lab1/implementation/dlmb_cntlr_wrapper.ngc_xst.xrpt
lab1/implementation/dlmb_cntlr_wrapper_vhdl.prj
lab1/implementation/dlmb_wrapper/
lab1/implementation/dlmb_wrapper.ngc
lab1/implementation/dlmb_wrapper.ngc_xst.xrpt
lab1/implementation/dlmb_wrapper_vhdl.prj
lab1/implementation/download.bit
lab1/implementation/fpga.flw
lab1/implementation/ilmb_cntlr_wrapper/
lab1/implementation/ilmb_cntlr_wrapper.ngc
lab1/implementation/ilmb_cntlr_wrapper.ngc_xst.xrpt
lab1/implementation/ilmb_cntlr_wrapper_vhdl.prj
lab1/implementation/ilmb_wrapper/
lab1/implementation/ilmb_wrapper.ngc
lab1/implementation/ilmb_wrapper.ngc_xst.xrpt
lab1/implementation/ilmb_wrapper_vhdl.prj
lab1/implementation/lmb_bram_wrapper/
lab1/implementation/lmb_bram_wrapper.ngc
lab1/implementation/lmb_bram_wrapper.ngc_xst.xrpt
lab1/implementation/lmb_bram_wrapper_vhdl.prj
lab1/implementation/mb_plb_wrapper/
lab1/implementation/mb_plb_wrapper.ngc
lab1/implementation/mb_plb_wrapper.ngc_xst.xrpt
lab1/implementation/mb_plb_wrapper_vhdl.prj
lab1/implementation/microblaze_0_wrapper/
lab1/implementation/microblaze_0_wrapper.ngc
lab1/implementation/microblaze_0_wrapper.ngc_xst.xrpt
lab1/implementation/microblaze_0_wrapper_vhdl.prj
lab1/implementation/micron_ram_util_bus_split_0_wrapper/
lab1/implementation/micron_ram_util_bus_split_0_wrapper.ngc
lab1/implementation/micron_ram_util_bus_split_0_wrapper.ngc_xst.xrpt
lab1/implementation/micron_ram_util_bus_split_0_wrapper_vhdl.prj
lab1/implementation/micron_ram_wrapper/
lab1/implementation/micron_ram_wrapper.ngc
lab1/implementation/micron_ram_wrapper.ngc_xst.xrpt
lab1/implementation/micron_ram_wrapper_vhdl.prj
lab1/implementation/netlist.lst
lab1/implementation/proc_sys_reset_0_wrapper/
lab1/implementation/proc_sys_reset_0_wrapper.ngc
lab1/implementation/proc_sys_reset_0_wrapper.ngc_xst.xrpt
lab1/implementation/proc_sys_reset_0_wrapper_vhdl.prj
lab1/implementation/rs232_port_wrapper/
lab1/implementation/rs232_port_wrapper.blc
lab1/implementation/rs232_port_wrapper.ngc
lab1/implementation/rs232_port_wrapper.ngc_xst.xrpt
lab1/implementation/rs232_port_wrapper/rs232_port_wrapper.ngc
lab1/implementation/rs232_port_wrapper/xlnx_auto_0.ise
lab1/implementation/rs232_port_wrapper/xlnx_auto_0_xdb/
lab1/implementation/rs232_port_wrapper/xlnx_auto_0_xdb/tmp/
lab1/implementation/rs232_port_wrapper_vhdl.prj
lab1/implementation/system.bgn
lab1/implementation/system.bit
lab1/implementation/system.bld
lab1/implementation/system.bmm
lab1/implementation/system.drc
lab1/implementation/system.ncd
lab1/implementation/system.ngc
lab1/implementation/system.ngc_xst.xrpt
lab1/implementation/system.ngd
lab1/implementation/system.pad
lab1/implementation/system.par
lab1/implementation/system.pcf
lab1/implementation/system.ptwx
lab1/implementation/system.twr
lab1/implementation/system.twx
lab1/implementation/system.ucf
lab1/implem

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