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文件名称:cpu

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    2.48mb
  • 已下载：
    0次
  • 提 供 者：
    熊****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

以ISE为平台设计的单时钟CPU，实现最基本的5条指令（R、LW、SW、BEQ、J）

-ISE as a platform to design single-clock CPU, 5 to achieve the most basic instructions (R, LW, SW, BEQ, J)
(系统自动生成,下载前可以参看下载内容)

下载文件列表

cpu/a.v
cpu/cpu.ise
cpu/cpu.ntrc_log
cpu/cpu.restore
cpu/cpu_top.bgn
cpu/cpu_top.bit
cpu/CPU_top.bld
cpu/CPU_top.cmd_log
cpu/cpu_top.drc
cpu/CPU_top.lso
cpu/CPU_top.ncd
cpu/CPU_top.ngc
cpu/CPU_top.ngd
cpu/CPU_top.ngr
cpu/CPU_top.pad
cpu/CPU_top.par
cpu/CPU_top.pcf
cpu/CPU_top.prj
cpu/CPU_top.ptwx
cpu/CPU_top.stx
cpu/CPU_top.syr
cpu/CPU_top.twr
cpu/CPU_top.twx
cpu/CPU_top.unroutes
cpu/CPU_top.ut
cpu/CPU_top.xpi
cpu/CPU_top.xst
cpu/CPU_top_guide.ncd
cpu/CPU_top_map.map
cpu/CPU_top_map.mrp
cpu/CPU_top_map.ncd
cpu/CPU_top_map.ngm
cpu/CPU_top_map.xrpt
cpu/CPU_top_ngdbuild.xrpt
cpu/CPU_top_pad.csv
cpu/CPU_top_pad.txt
cpu/CPU_top_par.xrpt
cpu/CPU_top_prev_built.ngd
cpu/CPU_top_summary.xml
cpu/CPU_top_usage.xml
cpu/CPU_top_xst.xrpt
cpu/cpu_xdb/cst.xbcd
cpu/cpu_xdb/tmp/ise/version
cpu/cpu_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject
cpu/cpu_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject_StrTbl
cpu/cpu_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/__stored_object_table__
cpu/cpu_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl
cpu/cpu_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl_StrTbl
cpu/cpu_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main
cpu/cpu_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main_StrTbl
cpu/cpu_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/NameMap
cpu/cpu_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/NameMap_StrTbl
cpu/cpu_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/__stored_objects__
cpu/cpu_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/__stored_objects___StrTbl
cpu/cpu_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/__stored_object_table__
cpu/cpu_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/GuiProjectData
cpu/cpu_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/GuiProjectData_StrTbl
cpu/cpu_xdb/tmp/ise/__REGISTRY__/Autonym/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/bitgen/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/common/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/cpldfit/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/Cs/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/dumpngdio/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/fuse/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/HDProject/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/hprep6/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/idem/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/map/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/netgen/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/ngc2edif/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/ngcbuild/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/ngdbuild/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/par/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/ProjectNavigator/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/ProjectNavigatorGui/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/runner/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/SrcCtrl/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/STE/bitgen/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/STE/map/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/STE/ngdbuild/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/STE/par/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/STE/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/STE/trce/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/STE/xst/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/taengine/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/trce/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/tsim/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/vhpcomp/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/vlogcomp/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/WebTalk/DesignDataCollection/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/WebTalk/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/xpwr/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/XSLTProcess/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/xst/regkeys
cpu/cpu_xdb/tmp/ise/__REGISTRY__/_ProjRepoInternal_/regkeys
cpu/cpu_xdb/tmp/ise.lock
cpu/c_dat_mem.asy
cpu/c_dat_mem.mif
cpu/c_dat_mem.ngc
cpu/c_dat_mem.sym
cpu/c_dat_mem.v
cpu/c_dat_mem.veo
cpu/c_dat_mem.vhd
cpu/c_dat_mem.vho
cpu/c_dat_mem.xco
cpu/c_dat_mem_flist.txt
cpu/c_dat_mem_readme.txt
cpu/c_dat_mem_xmdf.tcl
cpu/c_instr_mem.asy
cpu/c_instr_mem.mif
cpu/c_instr_mem.ngc
cpu/c_instr_mem.sym
cpu/c_instr_mem.v
cpu/c_instr_mem.veo
cpu/c_instr_mem.vhd
cpu/c_instr_mem.vho
cpu/c_instr_mem.xco
cpu/c_instr_mem_flist.txt
cpu/c_instr_mem_readme.txt
cpu/c_instr_mem_xmdf.tcl
cpu/dat_block_dat_block.coe
cpu/device_usage_statistics.html
cpu/instr_block_instr_block.coe
cpu/templates/coregen.xml
cpu/test.txt
cpu/top.ucf
cpu/xlnx_auto_0.ise
cpu/xlnx_auto_0_xdb/tmp/ise/version
cpu/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject
cpu/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject_StrTbl
cpu/xlnx_auto_0_xdb/tmp/ise/__REGISTRY__/Autonym/regkeys
cpu/xlnx_auto_0_xdb/tmp/ise/__REGISTRY__/common/regkeys
cpu/xlnx_auto_0_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/HDProject/regkeys
cpu/xlnx_auto_0_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/regkeys
cpu/xlnx_auto_0_xdb/tmp/ise/__REGISTRY__/STE/ngcbuild/regkeys
cpu/xlnx_auto_0_xdb/tmp/ise/__REGISTRY__/STE/regkeys
cpu/xlnx_auto_0_xdb/tmp/ise/__REGISTRY__/_ProjRepoInte

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