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文件名称:LCD_Controllerr

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    1.12mb
  • 已下载：
    0次
  • 提 供 者：
    edi***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

本设计详细介绍了使用altera的MAX II CPLD 设计并实现LCD控制器。-This document details the implementation of an LCD controller in an Altera®　MAX®　II CPLD.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/code/
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/code/lcd_controller.v
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/lcd_controller.cr.mti
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/lcd_controller.mpf
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/lcd_controller.v
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/lcd_testbench.v
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/transcript
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/vsim.wlf
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/wave.bmp
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/wave.do
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/@u@f@m2/
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/@u@f@m2/verilog.psm
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/@u@f@m2/_primary.dat
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/@u@f@m2/_primary.vhd
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/@u@f@m2_altufm_parallel_bmm/
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/@u@f@m2_altufm_parallel_bmm/verilog.psm
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/@u@f@m2_altufm_parallel_bmm/_primary.dat
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/@u@f@m2_altufm_parallel_bmm/_primary.vhd
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/divider/
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/divider/verilog.psm
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/divider/_primary.dat
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/divider/_primary.vhd
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/fsm/
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/fsm/verilog.psm
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/fsm/_primary.dat
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/fsm/_primary.vhd
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/lcd_controller/
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/lcd_controller/verilog.psm
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/lcd_controller/_primary.dat
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/lcd_controller/_primary.vhd
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/lcd_testbench/
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/lcd_testbench/verilog.psm
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/lcd_testbench/_primary.dat
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/lcd_testbench/_primary.vhd
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/_info
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.db_info
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.eco.cdb
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.sld_design_entry.sci
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/prev_cmp_lcd_controller.map.qmsg
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/prev_cmp_lcd_controller.qmsg
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/lcd_controller.asm.rpt
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/lcd_controller.cdf
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/lcd_controller.done
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/lcd_controller.dpf
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/lcd_controller.fit.rpt
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/lcd_controller.fit.smsg
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/lcd_controller.fit.summary
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/lcd_controller.flow.rpt
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/lcd_controller.map.rpt
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/lcd_controller.map.smsg
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/lcd_controller.map.summary
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/lcd_controller.pin
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/lcd_controller.pof
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/lcd_controller.qarlog
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/lcd_controller.qpf
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/lcd_controller.qsf
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/lcd_controller.qws
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/lcd_controller.tan.rpt
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/lcd_controller.v
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quar

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