文件名称:uart16550
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uart16550 IP核
HDL源代码,对设计自己uart的人员和学习串口通讯有一定的参考价值!其中,附有详细的所明文档!-uart16550 IP HDL source code, uart to design their own study of serial communication and has some reference value. Which, with detailed documentation as prescribed!
HDL源代码,对设计自己uart的人员和学习串口通讯有一定的参考价值!其中,附有详细的所明文档!-uart16550 IP HDL source code, uart to design their own study of serial communication and has some reference value. Which, with detailed documentation as prescribed!
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下载文件列表
uart16550/CVS/Root
uart16550/CVS/Repository
uart16550/CVS/Entries
uart16550/CVS
uart16550/Doc/CVS/Root
uart16550/Doc/CVS/Repository
uart16550/Doc/CVS/Entries
uart16550/Doc/CVS
uart16550/Doc/CHANGES.txt
uart16550/Doc/UART_spec.pdf
uart16550/Doc/src/CVS/Root
uart16550/Doc/src/CVS/Repository
uart16550/Doc/src/CVS/Entries
uart16550/Doc/src/CVS
uart16550/Doc/src/UART_spec.doc
uart16550/Doc/src
uart16550/Doc
uart16550/bench/CVS/Root
uart16550/bench/CVS/Repository
uart16550/bench/CVS/Entries
uart16550/bench/CVS
uart16550/bench/verilog/CVS/Root
uart16550/bench/verilog/CVS/Repository
uart16550/bench/verilog/CVS/Entries
uart16550/bench/verilog/CVS
uart16550/bench/verilog/readme.txt
uart16550/bench/verilog/uart_device.v
uart16550/bench/verilog/uart_device_utilities.v
uart16550/bench/verilog/uart_log.v
uart16550/bench/verilog/uart_test.v
uart16550/bench/verilog/uart_testbench.v
uart16550/bench/verilog/uart_testbench_defines.v
uart16550/bench/verilog/uart_testbench_utilities.v
uart16550/bench/verilog/uart_wb_utilities.v
uart16550/bench/verilog/vapi.log
uart16550/bench/verilog/wb_mast.v
uart16550/bench/verilog/wb_master_model.v
uart16550/bench/verilog/wb_model_defines.v
uart16550/bench/verilog/test_cases/CVS/Root
uart16550/bench/verilog/test_cases/CVS/Repository
uart16550/bench/verilog/test_cases/CVS/Entries
uart16550/bench/verilog/test_cases/CVS
uart16550/bench/verilog/test_cases/uart_int.v
uart16550/bench/verilog/test_cases
uart16550/bench/verilog
uart16550/bench/vhdl/CVS/Root
uart16550/bench/vhdl/CVS/Repository
uart16550/bench/vhdl/CVS/Entries
uart16550/bench/vhdl/CVS
uart16550/bench/vhdl/.keepme
uart16550/bench/vhdl
uart16550/bench
uart16550/fv/CVS/Root
uart16550/fv/CVS/Repository
uart16550/fv/CVS/Entries
uart16550/fv/CVS
uart16550/fv/.keepme
uart16550/fv
uart16550/lint/CVS/Root
uart16550/lint/CVS/Repository
uart16550/lint/CVS/Entries
uart16550/lint/CVS
uart16550/lint/bin/CVS/Root
uart16550/lint/bin/CVS/Repository
uart16550/lint/bin/CVS/Entries
uart16550/lint/bin/CVS
uart16550/lint/bin/.keepme
uart16550/lint/bin
uart16550/lint/log/CVS/Root
uart16550/lint/log/CVS/Repository
uart16550/lint/log/CVS/Entries
uart16550/lint/log/CVS
uart16550/lint/log/.keepme
uart16550/lint/log
uart16550/lint/out/CVS/Root
uart16550/lint/out/CVS/Repository
uart16550/lint/out/CVS/Entries
uart16550/lint/out/CVS
uart16550/lint/out/.keepme
uart16550/lint/out
uart16550/lint/run/CVS/Root
uart16550/lint/run/CVS/Repository
uart16550/lint/run/CVS/Entries
uart16550/lint/run/CVS
uart16550/lint/run/.keepme
uart16550/lint/run
uart16550/lint
uart16550/rtl/CVS/Root
uart16550/rtl/CVS/Repository
uart16550/rtl/CVS/Entries
uart16550/rtl/CVS
uart16550/rtl/verilog/CVS/Root
uart16550/rtl/verilog/CVS/Repository
uart16550/rtl/verilog/CVS/Entries
uart16550/rtl/verilog/CVS
uart16550/rtl/verilog/raminfr.v
uart16550/rtl/verilog/timescale.v
uart16550/rtl/verilog/uart_debug_if.v
uart16550/rtl/verilog/uart_defines.v
uart16550/rtl/verilog/uart_receiver.v
uart16550/rtl/verilog/uart_regs.v
uart16550/rtl/verilog/uart_rfifo.v
uart16550/rtl/verilog/uart_sync_flops.v
uart16550/rtl/verilog/uart_tfifo.v
uart16550/rtl/verilog/uart_top.v
uart16550/rtl/verilog/uart_transmitter.v
uart16550/rtl/verilog/uart_wb.v
uart16550/rtl/verilog
uart16550/rtl/verilog-backup/CVS/Root
uart16550/rtl/verilog-backup/CVS/Repository
uart16550/rtl/verilog-backup/CVS/Entries
uart16550/rtl/verilog-backup/CVS
uart16550/rtl/verilog-backup/timescale.v
uart16550/rtl/verilog-backup/uart_defines.v
uart16550/rtl/verilog-backup/uart_fifo.v
uart16550/rtl/verilog-backup/uart_receiver.v
uart16550/rtl/verilog-backup/uart_regs.v
uart16550/rtl/verilog-backup/uart_top.v
uart16550/rtl/verilog-backup/uart_transmitter.v
uart16550/rtl/verilog-backup/uart_wb.v
uart16550/rtl/verilog-backup
uart16550/rtl/vhdl/CVS/Root
uart16550/rtl/vhdl/CVS/Repository
uart16550/rtl/vhdl/CVS/Entries
uart16550/rtl/vhdl/CVS
uart16550/rtl/vhdl/.keepme
uart16550/rtl/vhdl
uart16550/rtl
uart16550/sim/CVS/Root
uart16550/sim/CVS/Repository
uart16550/sim/CVS/Entries
uart16550/sim/CVS
uart16550/sim/gate_sim/CVS/Root
uart16550/sim/gate_sim/CVS/Repository
uart16550/sim/gate_sim/CVS/Entries
uart16550/sim/gate_sim/CVS
uart16550/sim/gate_sim/bin/CVS/Root
uart16550/sim/gate_sim/bin/CVS/Repository
uart16550/sim/gate_sim/bin/CVS/Entries
uart16550/sim/gate_sim/bin/CVS
uart16550/sim/gate_sim/bin/.keepme
uart16550/sim/gate_sim/bin
uart16550/sim/gate_sim/log/CVS/Root
uart16550/sim/gate_sim/log/CVS/Repository
uart16550/sim/gate_sim/log/CVS/Entries
uart16550/sim/gate_sim/log/CVS
uart16550/sim/gate_sim/log/.keepme
uart16550/sim/gate_sim/log
uart16550/sim/gate_sim/out/CVS/Root
uart16550/sim/gate_sim/out/CVS/Repository
uart16550/sim/gate_sim/out/CVS/Entries
uart16550/sim/gate_sim/out/CVS
uart16550/sim/gate_sim/out/.keepme
uart16550/sim/gate_sim/out
uart16550/sim/gate_sim/run/CVS/Root
uart16550/sim/gate_sim/run/CVS/Repository
uart16550/sim/gate_sim/run/CVS/Entries
uart16550/sim/gate_sim/run/CVS
uart16550/sim/gate_sim/run/.keepme
uart16550/sim/gate_sim/run
uart16550/sim/gate_sim/src/CVS/Root
uart16550/sim/gate_sim/src/CVS/Repository
uart16550/sim/gate_sim/src/CVS/Entries
uart16550/sim/gate_si
uart16550/CVS/Repository
uart16550/CVS/Entries
uart16550/CVS
uart16550/Doc/CVS/Root
uart16550/Doc/CVS/Repository
uart16550/Doc/CVS/Entries
uart16550/Doc/CVS
uart16550/Doc/CHANGES.txt
uart16550/Doc/UART_spec.pdf
uart16550/Doc/src/CVS/Root
uart16550/Doc/src/CVS/Repository
uart16550/Doc/src/CVS/Entries
uart16550/Doc/src/CVS
uart16550/Doc/src/UART_spec.doc
uart16550/Doc/src
uart16550/Doc
uart16550/bench/CVS/Root
uart16550/bench/CVS/Repository
uart16550/bench/CVS/Entries
uart16550/bench/CVS
uart16550/bench/verilog/CVS/Root
uart16550/bench/verilog/CVS/Repository
uart16550/bench/verilog/CVS/Entries
uart16550/bench/verilog/CVS
uart16550/bench/verilog/readme.txt
uart16550/bench/verilog/uart_device.v
uart16550/bench/verilog/uart_device_utilities.v
uart16550/bench/verilog/uart_log.v
uart16550/bench/verilog/uart_test.v
uart16550/bench/verilog/uart_testbench.v
uart16550/bench/verilog/uart_testbench_defines.v
uart16550/bench/verilog/uart_testbench_utilities.v
uart16550/bench/verilog/uart_wb_utilities.v
uart16550/bench/verilog/vapi.log
uart16550/bench/verilog/wb_mast.v
uart16550/bench/verilog/wb_master_model.v
uart16550/bench/verilog/wb_model_defines.v
uart16550/bench/verilog/test_cases/CVS/Root
uart16550/bench/verilog/test_cases/CVS/Repository
uart16550/bench/verilog/test_cases/CVS/Entries
uart16550/bench/verilog/test_cases/CVS
uart16550/bench/verilog/test_cases/uart_int.v
uart16550/bench/verilog/test_cases
uart16550/bench/verilog
uart16550/bench/vhdl/CVS/Root
uart16550/bench/vhdl/CVS/Repository
uart16550/bench/vhdl/CVS/Entries
uart16550/bench/vhdl/CVS
uart16550/bench/vhdl/.keepme
uart16550/bench/vhdl
uart16550/bench
uart16550/fv/CVS/Root
uart16550/fv/CVS/Repository
uart16550/fv/CVS/Entries
uart16550/fv/CVS
uart16550/fv/.keepme
uart16550/fv
uart16550/lint/CVS/Root
uart16550/lint/CVS/Repository
uart16550/lint/CVS/Entries
uart16550/lint/CVS
uart16550/lint/bin/CVS/Root
uart16550/lint/bin/CVS/Repository
uart16550/lint/bin/CVS/Entries
uart16550/lint/bin/CVS
uart16550/lint/bin/.keepme
uart16550/lint/bin
uart16550/lint/log/CVS/Root
uart16550/lint/log/CVS/Repository
uart16550/lint/log/CVS/Entries
uart16550/lint/log/CVS
uart16550/lint/log/.keepme
uart16550/lint/log
uart16550/lint/out/CVS/Root
uart16550/lint/out/CVS/Repository
uart16550/lint/out/CVS/Entries
uart16550/lint/out/CVS
uart16550/lint/out/.keepme
uart16550/lint/out
uart16550/lint/run/CVS/Root
uart16550/lint/run/CVS/Repository
uart16550/lint/run/CVS/Entries
uart16550/lint/run/CVS
uart16550/lint/run/.keepme
uart16550/lint/run
uart16550/lint
uart16550/rtl/CVS/Root
uart16550/rtl/CVS/Repository
uart16550/rtl/CVS/Entries
uart16550/rtl/CVS
uart16550/rtl/verilog/CVS/Root
uart16550/rtl/verilog/CVS/Repository
uart16550/rtl/verilog/CVS/Entries
uart16550/rtl/verilog/CVS
uart16550/rtl/verilog/raminfr.v
uart16550/rtl/verilog/timescale.v
uart16550/rtl/verilog/uart_debug_if.v
uart16550/rtl/verilog/uart_defines.v
uart16550/rtl/verilog/uart_receiver.v
uart16550/rtl/verilog/uart_regs.v
uart16550/rtl/verilog/uart_rfifo.v
uart16550/rtl/verilog/uart_sync_flops.v
uart16550/rtl/verilog/uart_tfifo.v
uart16550/rtl/verilog/uart_top.v
uart16550/rtl/verilog/uart_transmitter.v
uart16550/rtl/verilog/uart_wb.v
uart16550/rtl/verilog
uart16550/rtl/verilog-backup/CVS/Root
uart16550/rtl/verilog-backup/CVS/Repository
uart16550/rtl/verilog-backup/CVS/Entries
uart16550/rtl/verilog-backup/CVS
uart16550/rtl/verilog-backup/timescale.v
uart16550/rtl/verilog-backup/uart_defines.v
uart16550/rtl/verilog-backup/uart_fifo.v
uart16550/rtl/verilog-backup/uart_receiver.v
uart16550/rtl/verilog-backup/uart_regs.v
uart16550/rtl/verilog-backup/uart_top.v
uart16550/rtl/verilog-backup/uart_transmitter.v
uart16550/rtl/verilog-backup/uart_wb.v
uart16550/rtl/verilog-backup
uart16550/rtl/vhdl/CVS/Root
uart16550/rtl/vhdl/CVS/Repository
uart16550/rtl/vhdl/CVS/Entries
uart16550/rtl/vhdl/CVS
uart16550/rtl/vhdl/.keepme
uart16550/rtl/vhdl
uart16550/rtl
uart16550/sim/CVS/Root
uart16550/sim/CVS/Repository
uart16550/sim/CVS/Entries
uart16550/sim/CVS
uart16550/sim/gate_sim/CVS/Root
uart16550/sim/gate_sim/CVS/Repository
uart16550/sim/gate_sim/CVS/Entries
uart16550/sim/gate_sim/CVS
uart16550/sim/gate_sim/bin/CVS/Root
uart16550/sim/gate_sim/bin/CVS/Repository
uart16550/sim/gate_sim/bin/CVS/Entries
uart16550/sim/gate_sim/bin/CVS
uart16550/sim/gate_sim/bin/.keepme
uart16550/sim/gate_sim/bin
uart16550/sim/gate_sim/log/CVS/Root
uart16550/sim/gate_sim/log/CVS/Repository
uart16550/sim/gate_sim/log/CVS/Entries
uart16550/sim/gate_sim/log/CVS
uart16550/sim/gate_sim/log/.keepme
uart16550/sim/gate_sim/log
uart16550/sim/gate_sim/out/CVS/Root
uart16550/sim/gate_sim/out/CVS/Repository
uart16550/sim/gate_sim/out/CVS/Entries
uart16550/sim/gate_sim/out/CVS
uart16550/sim/gate_sim/out/.keepme
uart16550/sim/gate_sim/out
uart16550/sim/gate_sim/run/CVS/Root
uart16550/sim/gate_sim/run/CVS/Repository
uart16550/sim/gate_sim/run/CVS/Entries
uart16550/sim/gate_sim/run/CVS
uart16550/sim/gate_sim/run/.keepme
uart16550/sim/gate_sim/run
uart16550/sim/gate_sim/src/CVS/Root
uart16550/sim/gate_sim/src/CVS/Repository
uart16550/sim/gate_sim/src/CVS/Entries
uart16550/sim/gate_si
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