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文件名称:MyDDR

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2012-11-16
  • 文件大小：
    8.99mb
  • 已下载：
    0次
  • 提 供 者：
    DM***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

分析FPGA如何控制DDR，这个方法是自己倍频而不是把倍频过程放进IPCORE里面处理-Analysis of how to control the FPGA DDR, this method is its frequency multiplier rather than the process inside the handle into the IPCORE
(系统自动生成,下载前可以参看下载内容)

下载文件列表

MyDDR/coregen_xil_3800_28.cgc
MyDDR/coregen_xil_3800_28.cgp
MyDDR/ddrm1.vhd
MyDDR/ipcore_dir/coregen.cgc
MyDDR/ipcore_dir/coregen.cgp
MyDDR/ipcore_dir/coregen.log
MyDDR/ipcore_dir/coregen.rsp
MyDDR/ipcore_dir/DDRCtrl/docs/768c.pdf
MyDDR/ipcore_dir/DDRCtrl/docs/adr_cntrl_timing_0.xls
MyDDR/ipcore_dir/DDRCtrl/docs/read_data_timing_0.xls
MyDDR/ipcore_dir/DDRCtrl/docs/ug086.pdf
MyDDR/ipcore_dir/DDRCtrl/docs/write_data_timing_0.xls
MyDDR/ipcore_dir/DDRCtrl/docs/xapp454_sp3.url
MyDDR/ipcore_dir/DDRCtrl/example_design/datasheet.txt
MyDDR/ipcore_dir/DDRCtrl/example_design/log.txt
MyDDR/ipcore_dir/DDRCtrl/example_design/mig.prj
MyDDR/ipcore_dir/DDRCtrl/example_design/par/create_ise.bat
MyDDR/ipcore_dir/DDRCtrl/example_design/par/DDRCtrl.ucf
MyDDR/ipcore_dir/DDRCtrl/example_design/par/icon_coregen.xco
MyDDR/ipcore_dir/DDRCtrl/example_design/par/ila_coregen.xco
MyDDR/ipcore_dir/DDRCtrl/example_design/par/ise_flow.bat
MyDDR/ipcore_dir/DDRCtrl/example_design/par/ise_run.txt
MyDDR/ipcore_dir/DDRCtrl/example_design/par/makeproj.bat
MyDDR/ipcore_dir/DDRCtrl/example_design/par/mem_interface_top.ut
MyDDR/ipcore_dir/DDRCtrl/example_design/par/readme.txt
MyDDR/ipcore_dir/DDRCtrl/example_design/par/rem_files.bat
MyDDR/ipcore_dir/DDRCtrl/example_design/par/set_ise_prop.tcl
MyDDR/ipcore_dir/DDRCtrl/example_design/par/vio_coregen.xco
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_addr_gen_0.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_cal_ctl.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_cal_top.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_cmd_fsm_0.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_cmp_data_0.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_controller_0.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_controller_iobs_0.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_data_gen_0.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_data_path_0.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_data_path_iobs_0.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_data_read_0.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_data_read_controller_0.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_data_write_0.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_dqs_delay_0.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_fifo_0_wr_en_0.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_fifo_1_wr_en_0.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_infrastructure.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_infrastructure_iobs_0.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_infrastructure_top0.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_iobs_0.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_main_0.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_parameters_0.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_ram8d_0.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_rd_gray_cntr.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_s3_dm_iob.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_s3_dqs_iob.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_s3_dq_iob.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_tap_dly.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_test_bench_0.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_top_0.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/rtl/DDRCtrl_wr_gray_cntr.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/sim/ddr_model.v
MyDDR/ipcore_dir/DDRCtrl/example_design/sim/ddr_model_parameters.vh
MyDDR/ipcore_dir/DDRCtrl/example_design/sim/sim.do
MyDDR/ipcore_dir/DDRCtrl/example_design/sim/sim_tb_top.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/sim/wiredly.vhd
MyDDR/ipcore_dir/DDRCtrl/example_design/synth/DDRCtrl.lso
MyDDR/ipcore_dir/DDRCtrl/example_design/synth/DDRCtrl.prj
MyDDR/ipcore_dir/DDRCtrl/example_design/synth/mem_interface_top_synp.sdc
MyDDR/ipcore_dir/DDRCtrl/example_design/synth/script_synp.tcl
MyDDR/ipcore_dir/DDRCtrl/user_design/datasheet.txt
MyDDR/ipcore_dir/DDRCtrl/user_design/log.txt
MyDDR/ipcore_dir/DDRCtrl/user_design/mig.prj
MyDDR/ipcore_dir/DDRCtrl/user_design/par/create_ise.bat
MyDDR/ipcore_dir/DDRCtrl/user_design/par/DDRCtrl.ucf
MyDDR/ipcore_dir/DDRCtrl/user_design/par/icon_coregen.xco
MyDDR/ipcore_dir/DDRCtrl/user_design/par/ila_coregen.xco
MyDDR/ipcore_dir/DDRCtrl/user_design/par/ise_flow.bat
MyDDR/ipcore_dir/DDRCtrl/user_design/par/ise_run.txt
MyDDR/ipcore_dir/DDRCtrl/user_design/par/makeproj.bat
MyDDR/ipcore_dir/DDRCtrl/user_design/par/mem_interface_top.ut
MyDDR/ipcore_dir/DDRCtrl/user_design/par/readme.txt
MyDDR/ipcore_dir/DDRCtrl/user_design/par/rem_files.bat
MyDDR/ipcore_dir/DDRCtrl/user_design/par/set_ise_prop.tcl
MyDDR/ipcore_dir/DDRCtrl/user_design/par/vio_coregen.xco
MyDDR/ipcore_dir/DDRCtrl/user_design/rtl/DDRCtrl.vhd
MyDDR/ipcore_dir/DDRCtrl/user_design/rtl/DDRCtrl_cal_ctl.vhd
MyDDR/ipcore_dir/DDRCtrl/user_design/rtl/DDRCtrl_cal_top.vhd
MyDDR/ipcore_dir/DDRCtrl/user_design/rtl/DDRCtrl_controller_0.vhd
MyDDR/ipcore_dir/DD

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