文件名称:uart_receive_send_verilog
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- 上传时间:2012-11-16
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文件大小:490.64kb
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自己写的串口quartus8.0工程,串口收发virilog程序,在EP1C3T144C8芯片验证运行成功,时钟频率50Mhz,波特率115200.-Own write serial quartus8.0-engineering serial transceiver virilog program runs successfully verified, in EP1C3T144C8 chip clock frequency of 50Mhz, baud rate 115200.
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下载文件列表
uart_receive_send_verilog/
uart_receive_send_verilog/async_receiver.bsf
uart_receive_send_verilog/async_transmitter.bsf
uart_receive_send_verilog/clk2div.v
uart_receive_send_verilog/cmd.bsf
uart_receive_send_verilog/Cmd.v
uart_receive_send_verilog/Cmd.v.bak
uart_receive_send_verilog/db/
uart_receive_send_verilog/db/prev_cmp_uart.asm.qmsg
uart_receive_send_verilog/db/prev_cmp_uart.fit.qmsg
uart_receive_send_verilog/db/prev_cmp_uart.map.qmsg
uart_receive_send_verilog/db/prev_cmp_uart.qmsg
uart_receive_send_verilog/db/prev_cmp_uart.sim.qmsg
uart_receive_send_verilog/db/prev_cmp_uart.tan.qmsg
uart_receive_send_verilog/db/uart.(0).cnf.cdb
uart_receive_send_verilog/db/uart.(0).cnf.hdb
uart_receive_send_verilog/db/uart.(1).cnf.cdb
uart_receive_send_verilog/db/uart.(1).cnf.hdb
uart_receive_send_verilog/db/uart.(2).cnf.cdb
uart_receive_send_verilog/db/uart.(2).cnf.hdb
uart_receive_send_verilog/db/uart.(5).cnf.cdb
uart_receive_send_verilog/db/uart.(5).cnf.hdb
uart_receive_send_verilog/db/uart.asm.qmsg
uart_receive_send_verilog/db/uart.cbx.xml
uart_receive_send_verilog/db/uart.cmp.bpm
uart_receive_send_verilog/db/uart.cmp.cdb
uart_receive_send_verilog/db/uart.cmp.ecobp
uart_receive_send_verilog/db/uart.cmp.hdb
uart_receive_send_verilog/db/uart.cmp.logdb
uart_receive_send_verilog/db/uart.cmp.rdb
uart_receive_send_verilog/db/uart.cmp.tdb
uart_receive_send_verilog/db/uart.cmp0.ddb
uart_receive_send_verilog/db/uart.db_info
uart_receive_send_verilog/db/uart.eco.cdb
uart_receive_send_verilog/db/uart.eds_overflow
uart_receive_send_verilog/db/uart.fit.qmsg
uart_receive_send_verilog/db/uart.hier_info
uart_receive_send_verilog/db/uart.hif
uart_receive_send_verilog/db/uart.map.bpm
uart_receive_send_verilog/db/uart.map.cdb
uart_receive_send_verilog/db/uart.map.ecobp
uart_receive_send_verilog/db/uart.map.hdb
uart_receive_send_verilog/db/uart.map.logdb
uart_receive_send_verilog/db/uart.map.qmsg
uart_receive_send_verilog/db/uart.map_bb.cdb
uart_receive_send_verilog/db/uart.map_bb.hdb
uart_receive_send_verilog/db/uart.map_bb.hdbx
uart_receive_send_verilog/db/uart.map_bb.logdb
uart_receive_send_verilog/db/uart.pre_map.cdb
uart_receive_send_verilog/db/uart.pre_map.hdb
uart_receive_send_verilog/db/uart.psp
uart_receive_send_verilog/db/uart.root_partition.cmp.atm
uart_receive_send_verilog/db/uart.root_partition.cmp.dfp
uart_receive_send_verilog/db/uart.root_partition.cmp.hdbx
uart_receive_send_verilog/db/uart.root_partition.cmp.logdb
uart_receive_send_verilog/db/uart.root_partition.cmp.rcf
uart_receive_send_verilog/db/uart.root_partition.map.atm
uart_receive_send_verilog/db/uart.root_partition.map.hdbx
uart_receive_send_verilog/db/uart.root_partition.map.info
uart_receive_send_verilog/db/uart.rtlv.hdb
uart_receive_send_verilog/db/uart.rtlv_sg.cdb
uart_receive_send_verilog/db/uart.rtlv_sg_swap.cdb
uart_receive_send_verilog/db/uart.sgdiff.cdb
uart_receive_send_verilog/db/uart.sgdiff.hdb
uart_receive_send_verilog/db/uart.signalprobe.cdb
uart_receive_send_verilog/db/uart.sim.cvwf
uart_receive_send_verilog/db/uart.sim.hdb
uart_receive_send_verilog/db/uart.sim.qmsg
uart_receive_send_verilog/db/uart.sim.rdb
uart_receive_send_verilog/db/uart.sld_design_entry.sci
uart_receive_send_verilog/db/uart.sld_design_entry_dsc.sci
uart_receive_send_verilog/db/uart.syn_hier_info
uart_receive_send_verilog/db/uart.tan.qmsg
uart_receive_send_verilog/db/uart.tis_db_list.ddb
uart_receive_send_verilog/db/uart.tmw_info
uart_receive_send_verilog/db/wed.wsf
uart_receive_send_verilog/div2clk.bsf
uart_receive_send_verilog/myfifo1.bsf
uart_receive_send_verilog/myfifo1.qip
uart_receive_send_verilog/myfifo1.v
uart_receive_send_verilog/myfifo1_bb.v
uart_receive_send_verilog/myfifo1_wave0.jpg
uart_receive_send_verilog/myfifo1_wave1.jpg
uart_receive_send_verilog/myfifo1_waveforms.html
uart_receive_send_verilog/ransmitter.v
uart_receive_send_verilog/ransmitter.v.bak
uart_receive_send_verilog/receiver.v
uart_receive_send_verilog/receiver.v.bak
uart_receive_send_verilog/uart.asm.rpt
uart_receive_send_verilog/uart.bdf
uart_receive_send_verilog/uart.cdf
uart_receive_send_verilog/uart.done
uart_receive_send_verilog/uart.dpf
uart_receive_send_verilog/uart.fit.rpt
uart_receive_send_verilog/uart.fit.smsg
uart_receive_send_verilog/uart.fit.summary
uart_receive_send_verilog/uart.flow.rpt
uart_receive_send_verilog/uart.map.rpt
uart_receive_send_verilog/uart.map.summary
uart_receive_send_verilog/uart.pin
uart_receive_send_verilog/uart.pof
uart_receive_send_verilog/uart.qpf
uart_receive_send_verilog/uart.qsf
uart_receive_send_verilog/uart.qws
uart_receive_send_verilog/uart.sim.rpt
uart_receive_send_verilog/uart.sof
uart_receive_send_verilog/uart.tan.rpt
uart_receive_send_verilog/uart.tan.summary
uart_receive_send_verilog/uart.vwf
uart_receive_send_verilog/async_receiver.bsf
uart_receive_send_verilog/async_transmitter.bsf
uart_receive_send_verilog/clk2div.v
uart_receive_send_verilog/cmd.bsf
uart_receive_send_verilog/Cmd.v
uart_receive_send_verilog/Cmd.v.bak
uart_receive_send_verilog/db/
uart_receive_send_verilog/db/prev_cmp_uart.asm.qmsg
uart_receive_send_verilog/db/prev_cmp_uart.fit.qmsg
uart_receive_send_verilog/db/prev_cmp_uart.map.qmsg
uart_receive_send_verilog/db/prev_cmp_uart.qmsg
uart_receive_send_verilog/db/prev_cmp_uart.sim.qmsg
uart_receive_send_verilog/db/prev_cmp_uart.tan.qmsg
uart_receive_send_verilog/db/uart.(0).cnf.cdb
uart_receive_send_verilog/db/uart.(0).cnf.hdb
uart_receive_send_verilog/db/uart.(1).cnf.cdb
uart_receive_send_verilog/db/uart.(1).cnf.hdb
uart_receive_send_verilog/db/uart.(2).cnf.cdb
uart_receive_send_verilog/db/uart.(2).cnf.hdb
uart_receive_send_verilog/db/uart.(5).cnf.cdb
uart_receive_send_verilog/db/uart.(5).cnf.hdb
uart_receive_send_verilog/db/uart.asm.qmsg
uart_receive_send_verilog/db/uart.cbx.xml
uart_receive_send_verilog/db/uart.cmp.bpm
uart_receive_send_verilog/db/uart.cmp.cdb
uart_receive_send_verilog/db/uart.cmp.ecobp
uart_receive_send_verilog/db/uart.cmp.hdb
uart_receive_send_verilog/db/uart.cmp.logdb
uart_receive_send_verilog/db/uart.cmp.rdb
uart_receive_send_verilog/db/uart.cmp.tdb
uart_receive_send_verilog/db/uart.cmp0.ddb
uart_receive_send_verilog/db/uart.db_info
uart_receive_send_verilog/db/uart.eco.cdb
uart_receive_send_verilog/db/uart.eds_overflow
uart_receive_send_verilog/db/uart.fit.qmsg
uart_receive_send_verilog/db/uart.hier_info
uart_receive_send_verilog/db/uart.hif
uart_receive_send_verilog/db/uart.map.bpm
uart_receive_send_verilog/db/uart.map.cdb
uart_receive_send_verilog/db/uart.map.ecobp
uart_receive_send_verilog/db/uart.map.hdb
uart_receive_send_verilog/db/uart.map.logdb
uart_receive_send_verilog/db/uart.map.qmsg
uart_receive_send_verilog/db/uart.map_bb.cdb
uart_receive_send_verilog/db/uart.map_bb.hdb
uart_receive_send_verilog/db/uart.map_bb.hdbx
uart_receive_send_verilog/db/uart.map_bb.logdb
uart_receive_send_verilog/db/uart.pre_map.cdb
uart_receive_send_verilog/db/uart.pre_map.hdb
uart_receive_send_verilog/db/uart.psp
uart_receive_send_verilog/db/uart.root_partition.cmp.atm
uart_receive_send_verilog/db/uart.root_partition.cmp.dfp
uart_receive_send_verilog/db/uart.root_partition.cmp.hdbx
uart_receive_send_verilog/db/uart.root_partition.cmp.logdb
uart_receive_send_verilog/db/uart.root_partition.cmp.rcf
uart_receive_send_verilog/db/uart.root_partition.map.atm
uart_receive_send_verilog/db/uart.root_partition.map.hdbx
uart_receive_send_verilog/db/uart.root_partition.map.info
uart_receive_send_verilog/db/uart.rtlv.hdb
uart_receive_send_verilog/db/uart.rtlv_sg.cdb
uart_receive_send_verilog/db/uart.rtlv_sg_swap.cdb
uart_receive_send_verilog/db/uart.sgdiff.cdb
uart_receive_send_verilog/db/uart.sgdiff.hdb
uart_receive_send_verilog/db/uart.signalprobe.cdb
uart_receive_send_verilog/db/uart.sim.cvwf
uart_receive_send_verilog/db/uart.sim.hdb
uart_receive_send_verilog/db/uart.sim.qmsg
uart_receive_send_verilog/db/uart.sim.rdb
uart_receive_send_verilog/db/uart.sld_design_entry.sci
uart_receive_send_verilog/db/uart.sld_design_entry_dsc.sci
uart_receive_send_verilog/db/uart.syn_hier_info
uart_receive_send_verilog/db/uart.tan.qmsg
uart_receive_send_verilog/db/uart.tis_db_list.ddb
uart_receive_send_verilog/db/uart.tmw_info
uart_receive_send_verilog/db/wed.wsf
uart_receive_send_verilog/div2clk.bsf
uart_receive_send_verilog/myfifo1.bsf
uart_receive_send_verilog/myfifo1.qip
uart_receive_send_verilog/myfifo1.v
uart_receive_send_verilog/myfifo1_bb.v
uart_receive_send_verilog/myfifo1_wave0.jpg
uart_receive_send_verilog/myfifo1_wave1.jpg
uart_receive_send_verilog/myfifo1_waveforms.html
uart_receive_send_verilog/ransmitter.v
uart_receive_send_verilog/ransmitter.v.bak
uart_receive_send_verilog/receiver.v
uart_receive_send_verilog/receiver.v.bak
uart_receive_send_verilog/uart.asm.rpt
uart_receive_send_verilog/uart.bdf
uart_receive_send_verilog/uart.cdf
uart_receive_send_verilog/uart.done
uart_receive_send_verilog/uart.dpf
uart_receive_send_verilog/uart.fit.rpt
uart_receive_send_verilog/uart.fit.smsg
uart_receive_send_verilog/uart.fit.summary
uart_receive_send_verilog/uart.flow.rpt
uart_receive_send_verilog/uart.map.rpt
uart_receive_send_verilog/uart.map.summary
uart_receive_send_verilog/uart.pin
uart_receive_send_verilog/uart.pof
uart_receive_send_verilog/uart.qpf
uart_receive_send_verilog/uart.qsf
uart_receive_send_verilog/uart.qws
uart_receive_send_verilog/uart.sim.rpt
uart_receive_send_verilog/uart.sof
uart_receive_send_verilog/uart.tan.rpt
uart_receive_send_verilog/uart.tan.summary
uart_receive_send_verilog/uart.vwf
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