UART/
UART/db/
UART/db/prev_cmp_uart.asm.qmsg
UART/db/prev_cmp_uart.eda.qmsg
UART/db/prev_cmp_uart.fit.qmsg
UART/db/prev_cmp_uart.map.qmsg
UART/db/prev_cmp_uart.qmsg
UART/db/prev_cmp_uart.tan.qmsg
UART/db/uart.(0).cnf.cdb
UART/db/uart.(0).cnf.hdb
UART/db/uart.(1).cnf.cdb
UART/db/uart.(1).cnf.hdb
UART/db/uart.(2).cnf.cdb
UART/db/uart.(2).cnf.hdb
UART/db/uart.(3).cnf.cdb
UART/db/uart.(3).cnf.hdb
UART/db/uart.(4).cnf.cdb
UART/db/uart.(4).cnf.hdb
UART/db/uart.(5).cnf.cdb
UART/db/uart.(5).cnf.hdb
UART/db/uart.ace_cmp.bpm
UART/db/uart.ace_cmp.cdb
UART/db/uart.ace_cmp.ecobp
UART/db/uart.ace_cmp.hdb
UART/db/uart.analyze_file.qmsg
UART/db/uart.asm.qmsg
UART/db/uart.asm_labs.ddb
UART/db/uart.cbx.xml
UART/db/uart.cmp.bpm
UART/db/uart.cmp.cdb
UART/db/uart.cmp.ecobp
UART/db/uart.cmp.hdb
UART/db/uart.cmp.kpt
UART/db/uart.cmp.logdb
UART/db/uart.cmp.rdb
UART/db/uart.cmp.tdb
UART/db/uart.cmp0.ddb
UART/db/uart.cmp2.ddb
UART/db/uart.cmp_merge.kpt
UART/db/uart.db_info
UART/db/uart.eco.cdb
UART/db/uart.eda.qmsg
UART/db/uart.fit.qmsg
UART/db/uart.hier_info
UART/db/uart.hif
UART/db/uart.lpc.html
UART/db/uart.lpc.rdb
UART/db/uart.lpc.txt
UART/db/uart.map.bpm
UART/db/uart.map.cdb
UART/db/uart.map.ecobp
UART/db/uart.map.hdb
UART/db/uart.map.kpt
UART/db/uart.map.logdb
UART/db/uart.map.qmsg
UART/db/uart.map_bb.cdb
UART/db/uart.map_bb.hdb
UART/db/uart.map_bb.logdb
UART/db/uart.pre_map.cdb
UART/db/uart.pre_map.hdb
UART/db/uart.rom0_TXD_150ab.hdl.mif
UART/db/uart.rtlv.hdb
UART/db/uart.rtlv_sg.cdb
UART/db/uart.rtlv_sg_swap.cdb
UART/db/uart.sgdiff.cdb
UART/db/uart.sgdiff.hdb
UART/db/uart.sld_design_entry.sci
UART/db/uart.sld_design_entry_dsc.sci
UART/db/uart.syn_hier_info
UART/db/uart.tan.qmsg
UART/db/uart.tis_db_list.ddb
UART/db/uart.tmw_info
UART/db/uart_global_asgn_op.abo
UART/div.bsf
UART/div.v
UART/div.v.bak
UART/incremental_db/
UART/incremental_db/compiled_partitions/
UART/incremental_db/compiled_partitions/uart.root_partition.cmp.atm
UART/incremental_db/compiled_partitions/uart.root_partition.cmp.dfp
UART/incremental_db/compiled_partitions/uart.root_partition.cmp.hdbx
UART/incremental_db/compiled_partitions/uart.root_partition.cmp.kpt
UART/incremental_db/compiled_partitions/uart.root_partition.cmp.logdb
UART/incremental_db/compiled_partitions/uart.root_partition.cmp.rcf
UART/incremental_db/compiled_partitions/uart.root_partition.map.atm
UART/incremental_db/compiled_partitions/uart.root_partition.map.dpi
UART/incremental_db/compiled_partitions/uart.root_partition.map.hdbx
UART/incremental_db/compiled_partitions/uart.root_partition.map.kpt
UART/incremental_db/README
UART/lcd.bsf
UART/lcd_clk.bsf
UART/rxd.bsf
UART/simulation/
UART/simulation/modelsim/
UART/simulation/modelsim/div.v
UART/simulation/modelsim/lcd.v
UART/simulation/modelsim/lcd.v.bak
UART/simulation/modelsim/lcd_clk.v
UART/simulation/modelsim/lcd_clk.v.bak
UART/simulation/modelsim/lcd_tb.v
UART/simulation/modelsim/lcd_tb.v.bak
UART/simulation/modelsim/rxd.v
UART/simulation/modelsim/rxd.v.bak
UART/simulation/modelsim/rxd_tb.v
UART/simulation/modelsim/rxd_tb.v.bak
UART/simulation/modelsim/tcl_stacktrace.txt
UART/simulation/modelsim/transcript
UART/simulation/modelsim/TXD.v
UART/simulation/modelsim/TXD.v.bak
UART/simulation/modelsim/TXD_tb.v
UART/simulation/modelsim/TXD_tb.v.bak
UART/simulation/modelsim/UART.cr.mti
UART/simulation/modelsim/UART.mpf
UART/simulation/modelsim/uart.sft
UART/simulation/modelsim/uart.vo
UART/simulation/modelsim/uart_modelsim.xrf
UART/simulation/modelsim/uart_v.sdo
UART/simulation/modelsim/vsim.wlf
UART/simulation/modelsim/work/
UART/simulation/modelsim/work/@t@x@d/
UART/simulation/modelsim/work/@t@x@d/verilog.asm
UART/simulation/modelsim/work/@t@x@d/_primary.dat
UART/simulation/modelsim/work/@t@x@d/_primary.vhd
UART/simulation/modelsim/work/@t@x@d_tb/
UART/simulation/modelsim/work/@t@x@d_tb/verilog.asm
UART/simulation/modelsim/work/@t@x@d_tb/_primary.dat
UART/simulation/modelsim/work/@t@x@d_tb/_primary.vhd
UART/simulation/modelsim/work/lcd/
UART/simulation/modelsim/work/lcd/verilog.asm
UART/simulation/modelsim/work/lcd/_primary.dat
UART/simulation/modelsim/work/lcd/_primary.vhd
UART/simulation/modelsim/work/lcd_tb/
UART/simulation/modelsim/work/lcd_tb/verilog.asm
UART/simulation/modelsim/work/lcd_tb/_primary.dat
UART/simulation/modelsim/work/lcd_tb/_primary.vhd
UART/simulation/modelsim/work/rxd/
UART/simulation/modelsim/work/rxd/verilog.asm
UART/simulation/modelsim/work/rxd/_primary.dat
UART/simulation/modelsim/work/rxd/_primary.vhd
UART/simulation/modelsim/work/rxd_tb/
UART/simulation/modelsim/work/rxd_tb/verilog.asm
UART/simulation/modelsim/work/rxd_tb/_primary.dat
UART/simulation/modelsim/work/rxd_tb/_primary.vhd
UART/simulation/modelsim/work/_info
UART/simulation/modelsim/work/_temp/
UART/TXD.bsf
UART/TXD.v
UART/TXD.v.bak
UART/uart.asm.rpt
UART/uart.bdf
UART/uart.done
UART/uart.dpf
UART/uart.eda.rpt
UART/uart.fit.rpt
UART/uart.fit.smsg
UART/uart.fit.summary
UART/uart.flow.rpt
UART/uart.map.rpt
UART/uart.map.smsg
UART/uart.map.summary
UART/uart.pin
UART/uart.pof
UART/uart.qpf
UART/uart.qsf
UART/uart.qws
UART/uart.sof
UART/uart.tan.rpt
UART/uart.tan.summary