分频器是指使输出信号频率为输入信号频率1/N的电子电路,N是分频系数。在许多电子设备中如电子钟、频率合成器等，需要各种不同频率的信号协同工作，常用的方法是以稳定度高的晶体振荡器为主振源，通过变换得到所需要的各种频率成分，分频器是一种主要变换手段。

本文当中，在分析研究和总结了分频技术的发展趋势的基础上，以实用、可靠、经济等设计原则为目标，介绍了基于FPGA的多种分频器的设计思路和实现方法。本设计采用EDA技术，以硬件描述语言VHDL为系统逻辑描述手段设计文件，在QuartusⅡ工具软件环境下，采用自顶向下的设计方法，由各个基本模块共同构建了一个基于FPGA的分频器。

本次设计实现了包括整数、半整数和小数这三种不同类型分频器的分频，在设计过程中，系统主芯片采用EP1C6Q240C8，各个模块在QuartusⅡ上进行编程调试和仿真通过后，在GW48-SOPC上进行了下载。通过对各个部分测试后表明均能正确分频，完成了对系统的软件和硬件的设计，达到了系统的设计要求。

-Frequency divider refers to the frequency of the output signal as the input signal 1/N of electronic circuits. N is the frequency coefficient. In many electronic equipments such as the electronic clock, frequency synthesizers, which need different frequency signals work together and common way is to use the stability of the crystal oscillator as vibration source by converting the frequency components all needed. The frequency divider is a major means of conversion.

In this paper, with the analytic study and review of trend basis of the technical frequency, a functional, reliable, economic and other design principles as the goal, this paper introduces a number of points frequency of the design and implementation based on FPGA. This design adopts the technology of EDA and hardware descr iption language VHDL as logical descr iption means of designing files. Under the environment of QuartusⅡ tools and the top-to-down approach, they build jointly a frequency divider by the basic modules base