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文件名称:ddr2_sdram_latest[1].tar

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [HTML]
  • 上传时间：
    2012-11-16
  • 文件大小：
    1.7mb
  • 已下载：
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  • 提 供 者：
    h****
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

ddr2 sdram 控制器的vhdl源码,并包括了ddr2 sdram芯片的仿真模型-DDR2 sdram controller VHDL source code and ddr2 sdram simulation module
(系统自动生成,下载前可以参看下载内容)

下载文件列表

ddr2_sdram/
ddr2_sdram/tags/
ddr2_sdram/branches/
ddr2_sdram/trunk/
ddr2_sdram/trunk/DDR2_readme.txt
ddr2_sdram/trunk/Top_Modul_VHDL_summary.html
ddr2_sdram/trunk/Top_Modul_VHDL.vhd
ddr2_sdram/trunk/Top_Modul_VHDL_bitgen.xwbt
ddr2_sdram/trunk/UB_Clock_UCF.ucf
ddr2_sdram/trunk/Top_Modul_VHDL_guide.ncd
ddr2_sdram/trunk/DDR2_liesmich.txt
ddr2_sdram/trunk/UB_Y-Led_UCF.ucf
ddr2_sdram/trunk/UB_Taster_BUS_UCF.ucf
ddr2_sdram/trunk/Prj_12_DDR2.gise
ddr2_sdram/trunk/iseconfig/
ddr2_sdram/trunk/iseconfig/Prj_12_DDR2.projectmgr
ddr2_sdram/trunk/iseconfig/Top_Modul_VHDL.xreport
ddr2_sdram/trunk/MIG_Settings/
ddr2_sdram/trunk/MIG_Settings/m02_Create_Design.JPG
ddr2_sdram/trunk/MIG_Settings/b01_part.JPG
ddr2_sdram/trunk/MIG_Settings/m08_Pins.JPG
ddr2_sdram/trunk/MIG_Settings/m07_Options2.JPG
ddr2_sdram/trunk/MIG_Settings/m05_Controller.JPG
ddr2_sdram/trunk/MIG_Settings/m11_License.JPG
ddr2_sdram/trunk/MIG_Settings/m03_FPGAs.JPG
ddr2_sdram/trunk/MIG_Settings/m06_Options.JPG
ddr2_sdram/trunk/MIG_Settings/b02_generation.JPG
ddr2_sdram/trunk/MIG_Settings/m04_Memory.JPG
ddr2_sdram/trunk/MIG_Settings/b04_mig_361.JPG
ddr2_sdram/trunk/MIG_Settings/m13_Design.JPG
ddr2_sdram/trunk/MIG_Settings/m10_Summary.JPG
ddr2_sdram/trunk/MIG_Settings/m01_customize.JPG
ddr2_sdram/trunk/MIG_Settings/m09_Bank.JPG
ddr2_sdram/trunk/MIG_Settings/m14_Coregen_Readme.JPG
ddr2_sdram/trunk/MIG_Settings/m12_PCB.JPG
ddr2_sdram/trunk/MIG_Settings/b03_advanced.JPG
ddr2_sdram/trunk/Prj12_Impact.ipf
ddr2_sdram/trunk/Prj12_Impact_xdb/
ddr2_sdram/trunk/Prj12_Impact_xdb/tmp/
ddr2_sdram/trunk/DDR2_Control_VHDL.vhd
ddr2_sdram/trunk/impact_impact.xwbt
ddr2_sdram/trunk/Buttons_VHDL.vhd
ddr2_sdram/trunk/webtalk_impact.xml
ddr2_sdram/trunk/DDR2_Read_VHDL.vhd
ddr2_sdram/trunk/_xmsgs/
ddr2_sdram/trunk/Prj_12_DDR2.xise
ddr2_sdram/trunk/UB_Schalter_BUS_UCF.ucf
ddr2_sdram/trunk/ipcore_dir/
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/par/
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/par/UB_DDR2_64bit_UCF.ucf
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_tap_dly.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_dqs_delay_0.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_rd_gray_cntr.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_parameters_0.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_data_read_controller_0.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_fifo_0_wr_en_0.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_data_write_0.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_infrastructure_iobs_0.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_iobs_0.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_s3_dq_iob.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_wr_gray_cntr.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_controller_iobs_0.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_data_path_iobs_0.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_infrastructure.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_fifo_1_wr_en_0.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_controller_0.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_data_read_0.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_infrastructure_top.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_s3_dm_iob.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_s3_dqs_iob.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_ram8d_0.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_top_0.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_data_path_0.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_clk_dcm.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_cal_ctl.vhd
ddr2_sdram/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_cal_top.vhd
ddr2_sdram/trunk/Clock_VHDL.vhd
ddr2_sdram/trunk/DDR2_Write_VHDL.vhd
ddr2_sdram/trunk/webtalk.log
ddr2_sdram/trunk/impact.xsl
ddr2_sdram/trunk/UB_Led_BUS_UCF.ucf

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