文件名称:switch
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- 上传时间:2012-11-16
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文件大小:559.25kb
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NETFPGA方面关于参考路由和参考交换机方面的代码,详细的描述了交换机实现的过程。-NETFPGA reference route and reference switches in the code, a detailed descr iption of the implementation process of the switch.
相关搜索: verilog switch
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下载文件列表
switch/add_hdr.v
switch/add_rm_hdr.v
switch/arbitrator.v
switch/cnet_sram_sm.v
switch/cpu_dma_queue.v
switch/cpu_dma_queue_no_regs.v
switch/cpu_dma_queue_regs.v
switch/cpu_dma_rx_queue.v
switch/cpu_dma_tx_queue.v
switch/decoder.v
switch/device_id_reg.v
switch/dump.v
switch/ethernet_parser.v
switch/ethernet_parser_32bit.v
switch/ethernet_parser_64bit.v
switch/fallthrough_small_fifo.v
switch/fallthrough_small_fifo_v2.v
switch/gene_ankur.ppt
switch/gig_eth_mac.v
switch/input_arbiter.v
switch/in_arb_regs.v
switch/lfsr32.v
switch/mac_cam_lut.v
switch/NetFPGA_Dev_2010_Scaling_the_NetFPGA_switch_using_Aurora_over_SATA.pdf
switch/nf2_core.v
switch/nf2_dma.v
switch/nf2_dma_bus_fsm.v
switch/nf2_dma_que_intfc.v
switch/nf2_dma_regs.v
switch/nf2_dma_sync.v
switch/nf2_mdio.v
switch/nf2_reg_grp.v
switch/nf2_top.v
switch/NF_All_defines.v
switch/op_lut_regs.v
switch/oq_header_parser.v
switch/oq_regs.v
switch/oq_regs_ctrl.v
switch/oq_regs_dual_port_ram.v
switch/oq_regs_eval_empty.v
switch/oq_regs_eval_full.v
switch/oq_regs_generic_reg_grp.v
switch/oq_regs_host_iface.v
switch/oq_reg_helper.v
switch/oq_reg_instances.v
switch/output_port_lookup.v
switch/output_queues.v
switch/priority_encoder.v
switch/pulse_synchronizer.v
switch/reg_grp.v
switch/remove_pkt.v
switch/rgmii_io.v
switch/rm_hdr.v
switch/rotate.v
switch/small_async_fifo.v
switch/small_fifo.v
switch/small_fifo_v2.v
switch/small_fifo_v3.v
switch/sram_arbiter.v
switch/sram_reg_access.v
switch/store_pkt.v
switch/udp_reg_master.v
switch/unused_reg.v
switch/user_data_path.v
switch
switch/add_rm_hdr.v
switch/arbitrator.v
switch/cnet_sram_sm.v
switch/cpu_dma_queue.v
switch/cpu_dma_queue_no_regs.v
switch/cpu_dma_queue_regs.v
switch/cpu_dma_rx_queue.v
switch/cpu_dma_tx_queue.v
switch/decoder.v
switch/device_id_reg.v
switch/dump.v
switch/ethernet_parser.v
switch/ethernet_parser_32bit.v
switch/ethernet_parser_64bit.v
switch/fallthrough_small_fifo.v
switch/fallthrough_small_fifo_v2.v
switch/gene_ankur.ppt
switch/gig_eth_mac.v
switch/input_arbiter.v
switch/in_arb_regs.v
switch/lfsr32.v
switch/mac_cam_lut.v
switch/NetFPGA_Dev_2010_Scaling_the_NetFPGA_switch_using_Aurora_over_SATA.pdf
switch/nf2_core.v
switch/nf2_dma.v
switch/nf2_dma_bus_fsm.v
switch/nf2_dma_que_intfc.v
switch/nf2_dma_regs.v
switch/nf2_dma_sync.v
switch/nf2_mdio.v
switch/nf2_reg_grp.v
switch/nf2_top.v
switch/NF_All_defines.v
switch/op_lut_regs.v
switch/oq_header_parser.v
switch/oq_regs.v
switch/oq_regs_ctrl.v
switch/oq_regs_dual_port_ram.v
switch/oq_regs_eval_empty.v
switch/oq_regs_eval_full.v
switch/oq_regs_generic_reg_grp.v
switch/oq_regs_host_iface.v
switch/oq_reg_helper.v
switch/oq_reg_instances.v
switch/output_port_lookup.v
switch/output_queues.v
switch/priority_encoder.v
switch/pulse_synchronizer.v
switch/reg_grp.v
switch/remove_pkt.v
switch/rgmii_io.v
switch/rm_hdr.v
switch/rotate.v
switch/small_async_fifo.v
switch/small_fifo.v
switch/small_fifo_v2.v
switch/small_fifo_v3.v
switch/sram_arbiter.v
switch/sram_reg_access.v
switch/store_pkt.v
switch/udp_reg_master.v
switch/unused_reg.v
switch/user_data_path.v
switch
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