文件名称:phase_test
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- 上传时间：2012-11-16
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文件大小：1.3mb
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VHDL,简易音频数字相位表的设计与实现 数字相位测量仪在工业领域中经常用到的一般测量工具，主要应用与同频率正弦信号间的相位差的测量显示。
本系统采用FPGA实现测量的核心部分，主要由数字鉴相、累加计数器、控制器以及寄存与显示译码电路组成。该系统硬件电路简单，整个系统采用硬件描述语言VHDL作为系统内部硬件结构的描述手段，在XILINX公司的ISE9.1的软件支持下完成。可以对20Hz~20kHz频率范围内的音频信号进行采样鉴相处理，并将数据传回FPGA进行相位差计数累加、测量运算，最后送显示译码电路显示，测相范围为 ，相位测量误差 < 。
经测试结果验证，本系统充分利用FPGA对数据的高速处理能力，是系统设计高效、可靠，处理速度快，稳定性高，易于实现。
-VHDL, simple audio digital phase Table Design and Implementation of the digital phase meter general measurement tools are often used in the industrial field, the measurement of the phase difference between the main application with the same frequency sinusoidal signal. The system uses the FPGA implementation of the core part of the measurement, mainly by the digital phase, cumulative counter, the decoding circuit of the controller as well as storage and display. The system hardware circuit is simple, and the entire system using hardware descr iption language VHDL system means a descr iption of the internal hardware structure, completed in the XILINX company ISE9.1 software support. The audio signal in the frequency range of 20Hz ~ 20kHz sampling KAM-phase process, and the data returned FPGA retardation counted accumulation measuring operation, and finally sent to the decoding circuit, the scope of the measurement phase, the phase measurement error < . The test results verify the full u
本系统采用FPGA实现测量的核心部分，主要由数字鉴相、累加计数器、控制器以及寄存与显示译码电路组成。该系统硬件电路简单，整个系统采用硬件描述语言VHDL作为系统内部硬件结构的描述手段，在XILINX公司的ISE9.1的软件支持下完成。可以对20Hz~20kHz频率范围内的音频信号进行采样鉴相处理，并将数据传回FPGA进行相位差计数累加、测量运算，最后送显示译码电路显示，测相范围为 ，相位测量误差 < 。
经测试结果验证，本系统充分利用FPGA对数据的高速处理能力，是系统设计高效、可靠，处理速度快，稳定性高，易于实现。
-VHDL, simple audio digital phase Table Design and Implementation of the digital phase meter general measurement tools are often used in the industrial field, the measurement of the phase difference between the main application with the same frequency sinusoidal signal. The system uses the FPGA implementation of the core part of the measurement, mainly by the digital phase, cumulative counter, the decoding circuit of the controller as well as storage and display. The system hardware circuit is simple, and the entire system using hardware descr iption language VHDL system means a descr iption of the internal hardware structure, completed in the XILINX company ISE9.1 software support. The audio signal in the frequency range of 20Hz ~ 20kHz sampling KAM-phase process, and the data returned FPGA retardation counted accumulation measuring operation, and finally sent to the decoding circuit, the scope of the measurement phase, the phase measurement error < . The test results verify the full u
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下载文件列表
phase_test/top.xpi
phase_test/top_pad.csv
phase_test/BCD_CODE.prj
phase_test/BCD_CODE.stx
phase_test/BCD_CODE.vhd
phase_test/BCD_CODE.xst
phase_test/phase_test.xise
phase_test/control.vhd
phase_test/controller.prj
phase_test/controller.stx
phase_test/controller.vhd
phase_test/controller.xst
phase_test/controller_vhdl.prj
phase_test/Counter_4096.prj
phase_test/Counter_4096.stx
phase_test/Counter_4096.vhd
phase_test/Counter_4096.xst
phase_test/Counter_4096_vhdl.prj
phase_test/device_usage_statistics.html
phase_test/display.prj
phase_test/display.stx
phase_test/display.vhd
phase_test/display.xst
phase_test/top.pad
phase_test/top_pad.txt
phase_test/top.ncd
phase_test/jianxiang.prj
phase_test/jianxiang.stx
phase_test/jianxiang.vhd
phase_test/jianxiang.xst
phase_test/jianxiang_vhdl.prj
phase_test/ll.ise_ISE_Backup
phase_test/ll.ntrc_log
phase_test/M_k_counter.prj
phase_test/M_k_counter.stx
phase_test/M_k_counter.vhd
phase_test/M_k_counter.xst
phase_test/top.unroutes
phase_test/BCD_CODE.spl
phase_test/pepExtractor.prj
phase_test/M_k_counter.spl
phase_test/phase_test.ise_ISE_Backup
phase_test/phase_test.ntrc_log
phase_test/top.bgn
phase_test/top.bit
phase_test/BCD_CODE.sym
phase_test/top.cmd_log
phase_test/top.drc
phase_test/top.lso
phase_test/__ISE_repository_phase_test.ise_.lock
phase_test/jianxiang.spl
phase_test/top.pcf
phase_test/top.prj
phase_test/top.spl
phase_test/top.stx
phase_test/top.sym
phase_test/top.syr
phase_test/top.twr
phase_test/top.twx
phase_test/top.ucf
phase_test/jianxiang.sym
phase_test/top.ut
phase_test/top.vhd
phase_test/display.spl
phase_test/top.xst
phase_test/top_fpe.prj
phase_test/top_guide.ncd
phase_test/M_k_counter.sym
phase_test/Counter_4096.spl
phase_test/top_prev_built.ngd
phase_test/top_summary.html
phase_test/Counter_4096.sym
phase_test/controller.spl
phase_test/__ISE_repository_ll.ise_.lock
phase_test/controller.sym
phase_test/display.sym
phase_test/_xmsgs/bitgen.xmsgs
phase_test/_xmsgs/fuse.xmsgs
phase_test/_xmsgs/vhpcomp.xmsgs
phase_test/_xmsgs/pn_parser.xmsgs
phase_test/_xmsgs/xst.xmsgs
phase_test/_xmsgs/ngdbuild.xmsgs
phase_test/_xmsgs/map.xmsgs
phase_test/_xmsgs/par.xmsgs
phase_test/_xmsgs/trce.xmsgs
phase_test/_ngo/netlist.lst
phase_test/top.vf
phase_test/top.sch
phase_test/top.jhd
phase_test/MK.vhd
phase_test/top_vhdl.prj
phase_test/top.ngr
phase_test/top.bld
phase_test/top.ngc
phase_test/top.ngd
phase_test/top_map.mrp
phase_test/top_map.map
phase_test/top_map.ngm
phase_test/top_map.ncd
phase_test/top_usage.xml
phase_test/top_summary.xml
phase_test/top.par
phase_test/iseconfig/top.xreport
phase_test/iseconfig/phase_test.projectmgr
phase_test/MK_vhd_beh.prj
phase_test/xilinxsim.ini
phase_test/MK_vhd_isim_beh.exe
phase_test/isim.cmd
phase_test/isim.log
phase_test/isimwavedata.xwv
phase_test/isim.hdlsourcefiles
phase_test/isim.tmp_save/_1
phase_test/phase_test_ise12migration.zip
phase_test/top_envsettings.html
phase_test/top.schPreview
phase_test/sch2HdlBatchFile
phase_test/pa.fromHdl.tcl
phase_test/planAhead_run_1/planAhead_run.log
phase_test/planAhead_run_1/planAhead.log
phase_test/planAhead_run_1/planAhead.jou
phase_test/planAhead_run_1/phase_test.data/sources_1/fileset.xml
phase_test/planAhead_run_1/phase_test.data/constrs_1/fileset.xml
phase_test/planAhead_run_1/phase_test.data/wt/webtalk_pa.xml
phase_test/planAhead_run_1/phase_test.ppr
phase_test/webtalk_pn.xml
phase_test/top_xst.xrpt
phase_test/xlnx_auto_0_xdb/cst.xbcd
phase_test/top_ngdbuild.xrpt
phase_test/top_map.xrpt
phase_test/top_fpga_editor.log
phase_test/top.ptwx
phase_test/top_par.xrpt
phase_test/pa.fromNetlist.tcl
phase_test/planAhead_run_2/planAhead_run.log
phase_test/planAhead_run_2/planAhead.log
phase_test/planAhead_run_2/planAhead.jou
phase_test/planAhead_run_2/phase_test.data/sources_1/fileset.xml
phase_test/planAhead_run_2/phase_test.data/constrs_1/fileset.xml
phase_test/planAhead_run_2/phase_test.data/runs/impl_1.psg
phase_test/planAhead_run_2/phase_test.data/runs/runs.xml
phase_test/planAhead_run_2/phase_test.data/wt/webtalk_pa.xml
phase_test/planAhead_run_2/phase_test.ppr
phase_test/phase_test.gise
phase_test/planAhead.ngc2edif.log
phase_test/M_k_counter_vhdl.prj
phase_test/BCD_CODE_vhdl.prj
phase_test/.lso
phase_test/display_vhdl.prj
phase_test/planAhead_run_1/phase_test.data/sources_1
phase_test/planAhead_run_1/phase_test.data/constrs_1
phase_test/planAhead_run_1/phase_test.data/wt
phase_test/planAhead_run_2/phase_test.data/sources_1
phase_test/planAhead_run_2/phase_test.data/constrs_1
phase_test/planAhead_run_2/phase_test.data/runs
phase_test/planAhead_run_2/phase_test.data/wt
phase_test/phase_test_xdb/tmp
phase_test/planAhead_run_1/phase_test.data
phase_test/planAhead_run_2/phase_test.data
phase_test/_xmsgs
phase_test/_ngo
phase_test/iseconfig
phase_test/isim.tmp_save
phase_test/phase_test_xdb
phase_test/planAhead_run_1
phase_test/xlnx_auto_0_xdb
phase_test/planAhead_run_2
phase_test
phase_test/top_pad.csv
phase_test/BCD_CODE.prj
phase_test/BCD_CODE.stx
phase_test/BCD_CODE.vhd
phase_test/BCD_CODE.xst
phase_test/phase_test.xise
phase_test/control.vhd
phase_test/controller.prj
phase_test/controller.stx
phase_test/controller.vhd
phase_test/controller.xst
phase_test/controller_vhdl.prj
phase_test/Counter_4096.prj
phase_test/Counter_4096.stx
phase_test/Counter_4096.vhd
phase_test/Counter_4096.xst
phase_test/Counter_4096_vhdl.prj
phase_test/device_usage_statistics.html
phase_test/display.prj
phase_test/display.stx
phase_test/display.vhd
phase_test/display.xst
phase_test/top.pad
phase_test/top_pad.txt
phase_test/top.ncd
phase_test/jianxiang.prj
phase_test/jianxiang.stx
phase_test/jianxiang.vhd
phase_test/jianxiang.xst
phase_test/jianxiang_vhdl.prj
phase_test/ll.ise_ISE_Backup
phase_test/ll.ntrc_log
phase_test/M_k_counter.prj
phase_test/M_k_counter.stx
phase_test/M_k_counter.vhd
phase_test/M_k_counter.xst
phase_test/top.unroutes
phase_test/BCD_CODE.spl
phase_test/pepExtractor.prj
phase_test/M_k_counter.spl
phase_test/phase_test.ise_ISE_Backup
phase_test/phase_test.ntrc_log
phase_test/top.bgn
phase_test/top.bit
phase_test/BCD_CODE.sym
phase_test/top.cmd_log
phase_test/top.drc
phase_test/top.lso
phase_test/__ISE_repository_phase_test.ise_.lock
phase_test/jianxiang.spl
phase_test/top.pcf
phase_test/top.prj
phase_test/top.spl
phase_test/top.stx
phase_test/top.sym
phase_test/top.syr
phase_test/top.twr
phase_test/top.twx
phase_test/top.ucf
phase_test/jianxiang.sym
phase_test/top.ut
phase_test/top.vhd
phase_test/display.spl
phase_test/top.xst
phase_test/top_fpe.prj
phase_test/top_guide.ncd
phase_test/M_k_counter.sym
phase_test/Counter_4096.spl
phase_test/top_prev_built.ngd
phase_test/top_summary.html
phase_test/Counter_4096.sym
phase_test/controller.spl
phase_test/__ISE_repository_ll.ise_.lock
phase_test/controller.sym
phase_test/display.sym
phase_test/_xmsgs/bitgen.xmsgs
phase_test/_xmsgs/fuse.xmsgs
phase_test/_xmsgs/vhpcomp.xmsgs
phase_test/_xmsgs/pn_parser.xmsgs
phase_test/_xmsgs/xst.xmsgs
phase_test/_xmsgs/ngdbuild.xmsgs
phase_test/_xmsgs/map.xmsgs
phase_test/_xmsgs/par.xmsgs
phase_test/_xmsgs/trce.xmsgs
phase_test/_ngo/netlist.lst
phase_test/top.vf
phase_test/top.sch
phase_test/top.jhd
phase_test/MK.vhd
phase_test/top_vhdl.prj
phase_test/top.ngr
phase_test/top.bld
phase_test/top.ngc
phase_test/top.ngd
phase_test/top_map.mrp
phase_test/top_map.map
phase_test/top_map.ngm
phase_test/top_map.ncd
phase_test/top_usage.xml
phase_test/top_summary.xml
phase_test/top.par
phase_test/iseconfig/top.xreport
phase_test/iseconfig/phase_test.projectmgr
phase_test/MK_vhd_beh.prj
phase_test/xilinxsim.ini
phase_test/MK_vhd_isim_beh.exe
phase_test/isim.cmd
phase_test/isim.log
phase_test/isimwavedata.xwv
phase_test/isim.hdlsourcefiles
phase_test/isim.tmp_save/_1
phase_test/phase_test_ise12migration.zip
phase_test/top_envsettings.html
phase_test/top.schPreview
phase_test/sch2HdlBatchFile
phase_test/pa.fromHdl.tcl
phase_test/planAhead_run_1/planAhead_run.log
phase_test/planAhead_run_1/planAhead.log
phase_test/planAhead_run_1/planAhead.jou
phase_test/planAhead_run_1/phase_test.data/sources_1/fileset.xml
phase_test/planAhead_run_1/phase_test.data/constrs_1/fileset.xml
phase_test/planAhead_run_1/phase_test.data/wt/webtalk_pa.xml
phase_test/planAhead_run_1/phase_test.ppr
phase_test/webtalk_pn.xml
phase_test/top_xst.xrpt
phase_test/xlnx_auto_0_xdb/cst.xbcd
phase_test/top_ngdbuild.xrpt
phase_test/top_map.xrpt
phase_test/top_fpga_editor.log
phase_test/top.ptwx
phase_test/top_par.xrpt
phase_test/pa.fromNetlist.tcl
phase_test/planAhead_run_2/planAhead_run.log
phase_test/planAhead_run_2/planAhead.log
phase_test/planAhead_run_2/planAhead.jou
phase_test/planAhead_run_2/phase_test.data/sources_1/fileset.xml
phase_test/planAhead_run_2/phase_test.data/constrs_1/fileset.xml
phase_test/planAhead_run_2/phase_test.data/runs/impl_1.psg
phase_test/planAhead_run_2/phase_test.data/runs/runs.xml
phase_test/planAhead_run_2/phase_test.data/wt/webtalk_pa.xml
phase_test/planAhead_run_2/phase_test.ppr
phase_test/phase_test.gise
phase_test/planAhead.ngc2edif.log
phase_test/M_k_counter_vhdl.prj
phase_test/BCD_CODE_vhdl.prj
phase_test/.lso
phase_test/display_vhdl.prj
phase_test/planAhead_run_1/phase_test.data/sources_1
phase_test/planAhead_run_1/phase_test.data/constrs_1
phase_test/planAhead_run_1/phase_test.data/wt
phase_test/planAhead_run_2/phase_test.data/sources_1
phase_test/planAhead_run_2/phase_test.data/constrs_1
phase_test/planAhead_run_2/phase_test.data/runs
phase_test/planAhead_run_2/phase_test.data/wt
phase_test/phase_test_xdb/tmp
phase_test/planAhead_run_1/phase_test.data
phase_test/planAhead_run_2/phase_test.data
phase_test/_xmsgs
phase_test/_ngo
phase_test/iseconfig
phase_test/isim.tmp_save
phase_test/phase_test_xdb
phase_test/planAhead_run_1
phase_test/xlnx_auto_0_xdb
phase_test/planAhead_run_2
phase_test
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