文件名称:I2C-Controller
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- 上传时间:2013-03-16
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文件大小:384.85kb
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已下载:0次
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介绍说明--下载内容来自于网络,使用问题请自行百度
I2C Controller for Serial EEPROMs,
包括源代码和说明文档,可以仿真-I2C Controller for Serial EEPROMs
包括源代码和说明文档,可以仿真-I2C Controller for Serial EEPROMs
(系统自动生成,下载前可以参看下载内容)
下载文件列表
RD1006/Docs/
RD1006/Docs/i2cspec1.pdf
RD1006/Docs/rd1006.pdf
RD1006/Docs/rd1006_readme.txt
RD1006/Project/
RD1006/Project/i2c_seprom.h
RD1006/Project/i2c_seprom.lci
RD1006/Project/i2c_seprom.lpf
RD1006/Project/i2c_tb_tf.udo
RD1006/Project/i2c_tb_tfa.udo
RD1006/Project/i2c_tb_tff.udo
RD1006/Project/i2c_tb_tffa.udo
RD1006/Project/i2c_tb_vhd.udo
RD1006/Project/i2c_tb_vhda.udo
RD1006/Project/i2c_tb_vhdaf.udo
RD1006/Project/i2c_tb_vhdf.udo
RD1006/Simulation/
RD1006/Simulation/verilog/
RD1006/Simulation/verilog/rtl_verilog.do
RD1006/Simulation/verilog/timing_verilog.do
RD1006/Simulation/vhdl/
RD1006/Simulation/vhdl/rtl_vhdl.do
RD1006/Simulation/vhdl/timing_vhdl.do
RD1006/Source/
RD1006/Source/verilog/
RD1006/Source/verilog/i2c.v
RD1006/Source/verilog/i2c_clk.v
RD1006/Source/verilog/i2c_rreg.v
RD1006/Source/verilog/i2c_st.v
RD1006/Source/verilog/i2c_wreg.v
RD1006/Source/vhdl/
RD1006/Source/vhdl/i2c.vhd
RD1006/Source/vhdl/i2c_clk.vhd
RD1006/Source/vhdl/i2c_rreg.vhd
RD1006/Source/vhdl/i2c_st.vhd
RD1006/Source/vhdl/i2c_wreg.vhd
RD1006/Testbench/
RD1006/Testbench/verilog/
RD1006/Testbench/verilog/clk_rst.v
RD1006/Testbench/verilog/i2c_slave.v
RD1006/Testbench/verilog/i2c_tb.v
RD1006/Testbench/verilog/micro.v
RD1006/Testbench/vhdl/
RD1006/Testbench/vhdl/i2c_tb.vhd
RD1006/
RD1006/Docs/i2cspec1.pdf
RD1006/Docs/rd1006.pdf
RD1006/Docs/rd1006_readme.txt
RD1006/Project/
RD1006/Project/i2c_seprom.h
RD1006/Project/i2c_seprom.lci
RD1006/Project/i2c_seprom.lpf
RD1006/Project/i2c_tb_tf.udo
RD1006/Project/i2c_tb_tfa.udo
RD1006/Project/i2c_tb_tff.udo
RD1006/Project/i2c_tb_tffa.udo
RD1006/Project/i2c_tb_vhd.udo
RD1006/Project/i2c_tb_vhda.udo
RD1006/Project/i2c_tb_vhdaf.udo
RD1006/Project/i2c_tb_vhdf.udo
RD1006/Simulation/
RD1006/Simulation/verilog/
RD1006/Simulation/verilog/rtl_verilog.do
RD1006/Simulation/verilog/timing_verilog.do
RD1006/Simulation/vhdl/
RD1006/Simulation/vhdl/rtl_vhdl.do
RD1006/Simulation/vhdl/timing_vhdl.do
RD1006/Source/
RD1006/Source/verilog/
RD1006/Source/verilog/i2c.v
RD1006/Source/verilog/i2c_clk.v
RD1006/Source/verilog/i2c_rreg.v
RD1006/Source/verilog/i2c_st.v
RD1006/Source/verilog/i2c_wreg.v
RD1006/Source/vhdl/
RD1006/Source/vhdl/i2c.vhd
RD1006/Source/vhdl/i2c_clk.vhd
RD1006/Source/vhdl/i2c_rreg.vhd
RD1006/Source/vhdl/i2c_st.vhd
RD1006/Source/vhdl/i2c_wreg.vhd
RD1006/Testbench/
RD1006/Testbench/verilog/
RD1006/Testbench/verilog/clk_rst.v
RD1006/Testbench/verilog/i2c_slave.v
RD1006/Testbench/verilog/i2c_tb.v
RD1006/Testbench/verilog/micro.v
RD1006/Testbench/vhdl/
RD1006/Testbench/vhdl/i2c_tb.vhd
RD1006/
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