文件名称:_12_DA[TLC5615]_1
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文件大小:2.85mb
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通过DA输出正弦波,频率1KHz
ad采用的是TLC5615
输出的正弦波与理想波形基本一样-DA output sine wave frequency 1KHz
The ad is TLC5615
The sine wave output with the ideal waveform is basically the same
ad采用的是TLC5615
输出的正弦波与理想波形基本一样-DA output sine wave frequency 1KHz
The ad is TLC5615
The sine wave output with the ideal waveform is basically the same
(系统自动生成,下载前可以参看下载内容)
下载文件列表
_12_DA[TLC5615]_1/Modelsim/DAC.cr.mti
_12_DA[TLC5615]_1/Modelsim/DAC.mpf
_12_DA[TLC5615]_1/Modelsim/sim.do
_12_DA[TLC5615]_1/Modelsim/vsim.wlf
_12_DA[TLC5615]_1/Modelsim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/verilog.asm
_12_DA[TLC5615]_1/Modelsim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/verilog.asm
_12_DA[TLC5615]_1/Modelsim/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/@d@a@c_5615_@c@t@l/verilog.asm
_12_DA[TLC5615]_1/Modelsim/work/@d@a@c_5615_@c@t@l/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/@d@a@c_5615_@c@t@l/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/@d@a@c_5615_@c@t@l_tb/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/@d@a@c_5615_@c@t@l_tb/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/@d@a@c_@s@i@n@e_1@k/verilog.asm
_12_DA[TLC5615]_1/Modelsim/work/@d@a@c_@s@i@n@e_1@k/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/@d@a@c_@s@i@n@e_1@k/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/@d@a@c_@s@i@n@e_1@k_tb/verilog.asm
_12_DA[TLC5615]_1/Modelsim/work/@d@a@c_@s@i@n@e_1@k_tb/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/@d@a@c_@s@i@n@e_1@k_tb/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/@m@f_cycloneiii_pll/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/@m@f_cycloneiii_pll/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/@m@f_pll_reg/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/@m@f_pll_reg/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/@m@f_stratixiii_pll/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/@m@f_stratixiii_pll/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/@m@f_stratixii_pll/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/@m@f_stratixii_pll/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/@m@f_stratix_pll/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/@m@f_stratix_pll/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/@r@o@m/verilog.asm
_12_DA[TLC5615]_1/Modelsim/work/@r@o@m/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/@r@o@m/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/alt3pram/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/alt3pram/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altaccumulate/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altaccumulate/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altcam/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altcam/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altclklock/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altclklock/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altddio_bidir/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altddio_bidir/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altddio_in/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altddio_in/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altddio_out/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altddio_out/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altdpram/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altdpram/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altdq_dqs/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altdq_dqs/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altera_std_synchronizer/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altera_std_synchronizer/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altera_std_synchronizer_bundle/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altera_std_synchronizer_bundle/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altfp_mult/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altfp_mult/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altlvds_rx/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altlvds_rx/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altlvds_tx/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altlvds_tx/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altmult_accum/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altmult_accum/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altmult_add/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altmult_add/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altparallel_flash_loader/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altparallel_flash_loader/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altpll/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altpll/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altqpram/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altqpram/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altserial_flash_loader/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altserial_flash_loader/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altshift_taps/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altshift_taps/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altsource_probe/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altsource_probe/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altsqrt/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altsqrt/_primary.vhd
_12_DA[TLC561
_12_DA[TLC5615]_1/Modelsim/DAC.mpf
_12_DA[TLC5615]_1/Modelsim/sim.do
_12_DA[TLC5615]_1/Modelsim/vsim.wlf
_12_DA[TLC5615]_1/Modelsim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/verilog.asm
_12_DA[TLC5615]_1/Modelsim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/verilog.asm
_12_DA[TLC5615]_1/Modelsim/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/@d@a@c_5615_@c@t@l/verilog.asm
_12_DA[TLC5615]_1/Modelsim/work/@d@a@c_5615_@c@t@l/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/@d@a@c_5615_@c@t@l/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/@d@a@c_5615_@c@t@l_tb/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/@d@a@c_5615_@c@t@l_tb/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/@d@a@c_@s@i@n@e_1@k/verilog.asm
_12_DA[TLC5615]_1/Modelsim/work/@d@a@c_@s@i@n@e_1@k/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/@d@a@c_@s@i@n@e_1@k/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/@d@a@c_@s@i@n@e_1@k_tb/verilog.asm
_12_DA[TLC5615]_1/Modelsim/work/@d@a@c_@s@i@n@e_1@k_tb/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/@d@a@c_@s@i@n@e_1@k_tb/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/@m@f_cycloneiii_pll/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/@m@f_cycloneiii_pll/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/@m@f_pll_reg/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/@m@f_pll_reg/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/@m@f_stratixiii_pll/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/@m@f_stratixiii_pll/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/@m@f_stratixii_pll/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/@m@f_stratixii_pll/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/@m@f_stratix_pll/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/@m@f_stratix_pll/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/@r@o@m/verilog.asm
_12_DA[TLC5615]_1/Modelsim/work/@r@o@m/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/@r@o@m/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/alt3pram/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/alt3pram/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altaccumulate/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altaccumulate/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altcam/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altcam/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altclklock/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altclklock/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altddio_bidir/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altddio_bidir/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altddio_in/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altddio_in/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altddio_out/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altddio_out/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altdpram/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altdpram/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altdq_dqs/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altdq_dqs/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altera_std_synchronizer/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altera_std_synchronizer/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altera_std_synchronizer_bundle/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altera_std_synchronizer_bundle/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altfp_mult/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altfp_mult/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altlvds_rx/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altlvds_rx/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altlvds_tx/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altlvds_tx/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altmult_accum/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altmult_accum/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altmult_add/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altmult_add/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altparallel_flash_loader/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altparallel_flash_loader/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altpll/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altpll/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altqpram/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altqpram/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altserial_flash_loader/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altserial_flash_loader/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altshift_taps/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altshift_taps/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altsource_probe/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altsource_probe/_primary.vhd
_12_DA[TLC5615]_1/Modelsim/work/altsqrt/_primary.dat
_12_DA[TLC5615]_1/Modelsim/work/altsqrt/_primary.vhd
_12_DA[TLC561
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